coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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1797 discussions

Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth Mercury White (la...
by Angel Pons (Code Review) 10 Feb '20

10 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 ) Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) ...................................................................... Patch Set 10: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/37565/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37565/10//COMMIT_MSG@23 PS10, Line 23: APCI ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 10 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Sun, 09 Feb 2020 23:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Angel Pons (Code Review) 10 Feb '20

10 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 ) Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 14 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 09 Feb 2020 23:24:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 ) Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 14 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 09 Feb 2020 22:10:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth Mercury White (la...
by Mimoja (Code Review) 09 Feb '20

09 Feb '20

Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37565 to look at the new patch set (#10). Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) ...................................................................... mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) The Razer Blade Stealth Mercury White is a Ice Lake system using: - Intel i7-1065G7 (Ice Lake with Iris Plus GPU) - ITE IT8320VG EC (currently unsupported in coreboot) - Samsung M981 MZ-VLKB2560 256GB NVMe SSD - Four Samsung K4UBE3D4AM-GHCL LPDDR4 chips - Integrated TitanRidge Thunderbolt 3 / 4 controller - Two Realtek Audio chips: - ALC298 for the audio jack - ALC1306 for the speakers - Parade PS8802 USB Type-C Host Switch - Unlabled Intel USB Type-C Thunderbolt Switch This commit includes basic ram init and devicetree configuration and therefore everything required to call into the payload. It is missing APCI, power and advanced device initialization as well as EC support which should be included on its own in a future commit. Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/blade_stealth_icl/Kconfig A src/mainboard/razer/blade_stealth_icl/Kconfig.name A src/mainboard/razer/blade_stealth_icl/Makefile.inc A src/mainboard/razer/blade_stealth_icl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_icl/board_info.txt A src/mainboard/razer/blade_stealth_icl/bootblock.c A src/mainboard/razer/blade_stealth_icl/devicetree.cb A src/mainboard/razer/blade_stealth_icl/dsdt.asl A src/mainboard/razer/blade_stealth_icl/gpio.h A src/mainboard/razer/blade_stealth_icl/hda_verb.c A src/mainboard/razer/blade_stealth_icl/ramstage.c A src/mainboard/razer/blade_stealth_icl/romstage.c A src/mainboard/razer/blade_stealth_icl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_icl/spd/samsung_K4UBE3D4AA.spd.hex 14 files changed, 649 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37565/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 10 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth Mercury White (la...
by Mimoja (Code Review) 09 Feb '20

09 Feb '20

Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37565 to look at the new patch set (#9). Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) ...................................................................... mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) The Razer Blade Stealth Mercury White is a Ice Lake system using: - Intel i7-1065G7 (Ice Lake with Iris Plus GPU) - ITE IT8320VG EC (currently unsupported) - Samsung M981 MZ-VLKB2560 256GB NVMe SSD - Four Samsung K4UBE3D4AM-GHCL LPDDR4 chips - Integrated TitanRidge Thunderbolt 3 controller - Two Realtek Audio chips: - ALC298 for the audio jack - ALC1306 for the speaks - Parade PS8802 USB-C Host Switch - Intel USB-C Thunderbolt Switch This commit includes basic ram init and devicetree configuration and therefore everything required to call into the payload. It is missing APCI, power and advanced device initialization as well as EC support which should included on its own in the future. Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/blade_stealth_icl/Kconfig A src/mainboard/razer/blade_stealth_icl/Kconfig.name A src/mainboard/razer/blade_stealth_icl/Makefile.inc A src/mainboard/razer/blade_stealth_icl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_icl/board_info.txt A src/mainboard/razer/blade_stealth_icl/bootblock.c A src/mainboard/razer/blade_stealth_icl/devicetree.cb A src/mainboard/razer/blade_stealth_icl/dsdt.asl A src/mainboard/razer/blade_stealth_icl/gpio.h A src/mainboard/razer/blade_stealth_icl/hda_verb.c A src/mainboard/razer/blade_stealth_icl/ramstage.c A src/mainboard/razer/blade_stealth_icl/romstage.c A src/mainboard/razer/blade_stealth_icl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_icl/spd/samsung_K4UBE3D4AA.spd.hex 14 files changed, 649 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37565/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] Add Razer Blade Stealth IceLake Mercury White (late 2019)
by Mimoja (Code Review) 09 Feb '20

09 Feb '20

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 ) Change subject: [WIP] Add Razer Blade Stealth IceLake Mercury White (late 2019) ...................................................................... Patch Set 8: (24 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/37565/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37565/2//COMMIT_MSG@7 PS2, Line 7: IceLake > thx Done https://review.coreboot.org/c/coreboot/+/37565/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37565/3//COMMIT_MSG@11 PS3, Line 11: SuperIO > ITE website disagrees: […] Done https://review.coreboot.org/c/coreboot/+/37565/3//COMMIT_MSG@13 PS3, Line 13: Two > Only two LPDDR4 chips? Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/Kconfig: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 37: UART_FOR_CONSOLE > Where is the UART routed to? Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/Makefile.inc: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 22: CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB > This is enforced by the mainboard selection. Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/acpi/mainboard.asl: PS3: > Is this file needed, or is it a stub? Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/acpi_tables.c: PS3: > There's a change dropping these empty files Done https://review.coreboot.org/c/coreboot/+/37565/2/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/board_info.txt: https://review.coreboot.org/c/coreboot/+/37565/2/src/mainboard/razer/blade_… PS2, Line 2: Board name: L > I had a contact @ razer who told me the codename. And i forgot.... […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 39: Pch > nit: PCH Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 164: Enable > Really? Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 189: end > Please align these `end`. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 298: end > Another misalignment around here Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/dsdt.asl: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 28: // Some generic macros > I got rid of these comments recently! Please don't add them again Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 34: // CPU > This comment doesn't really add any value, does it? Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 36: : Scope (\_SB) { : Device (PCI0) > Device (\_SB. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 45: // Chipset specific sleep states > I removed these comments as well. The sleepstates are no longer specific to each chipset. Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 49: #include "acpi/mainboard.asl" > If you don't use that file, this can be dropped Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/hda_verb.h: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 22: /* ALC 700 */ : 0x10EC0700, 0xFFFFFFFF, 0x00000023, > You can add comments to these values. Also, please use lowercase for hex constants. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 25: 0x10EC10F2 > You can also put this value in place of the 0xffffffff above Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 25: AZALIA_PIN_CFG(0, 0x01, 0x00000000), > Looks bogus. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 26: AZALIA_PIN_CFG(0, 0x12, 0x40000000), AZALIA_PIN_CFG(0, 0x13, 0x40000000), : AZALIA_PIN_CFG(0, 0x14, 0x411111F0), AZALIA_PIN_CFG(0, 0x15, 0x411111F0), : AZALIA_PIN_CFG(0, 0x16, 0x411111F0), AZALIA_PIN_CFG(0, 0x17, 0x90170110), : AZALIA_PIN_CFG(0, 0x18, 0x411111F0), AZALIA_PIN_CFG(0, 0x19, 0x04A11030), : AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), : AZALIA_PIN_CFG(0, 0x1D, 0x40622005), AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), : AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), AZALIA_PIN_CFG(0, 0x21, 0x04211020), : AZALIA_PIN_CFG(0, 0x29, 0x411111F0), > Please put these on individual lines. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 40: // Widget node 0X20 for ALC1305 20160603 update > Are all of these hex spells applicable to the ALC700? If so, please group them in quadruples (groups […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/hda_verb.c: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 15: #include "hda_verb.h" > Why don't you just put the hda_verb. […] Done https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… File src/mainboard/razer/blade_stealth_icl/romstage.c: https://review.coreboot.org/c/coreboot/+/37565/3/src/mainboard/razer/blade_… PS3, Line 28: // Only one memory setup exists > Please use consistent comment styles Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 8 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 09 Feb 2020 21:45:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mimoja <coreboot(a)mimoja.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by Furquan Shaikh (Code Review) 09 Feb '20

09 Feb '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... Patch Set 17: Code-Review+1 (4 comments) https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… PS17, Line 34: pmc_ipc_cmd Having a comment indicating how this is supposed to be used will be helpful. https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… PS17, Line 257: cmd Can you please add a comment indicating what the params are supposed to be? Especially for cmd, this is really pmc_ipc_cmd which users will have to create a union for when passing in the cmd parameter. https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… PS17, Line 257: struct const https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc… PS17, Line 633: struct const -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 17 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 09 Feb 2020 21:16:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] sb/intel/lynxpoint: Isolate _HID and _ADR
by Angel Pons (Code Review) 09 Feb '20

09 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38802 ) Change subject: [WIP] sb/intel/lynxpoint: Isolate _HID and _ADR ...................................................................... [WIP] sb/intel/lynxpoint: Isolate _HID and _ADR That way, newer IASL won't complain about it. Change-Id: I086730102e68fd709e8d3bbcfa42855ff0a0ab99 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38802/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..ea0339d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -125,6 +125,10 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) +} + +Scope (SDMA) +{ Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -163,6 +167,10 @@ Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) +} + +Scope (I2C0) +{ Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) @@ -245,6 +253,10 @@ Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) +} + +Scope (I2C1) +{ Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) @@ -327,6 +339,10 @@ Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) +} + +Scope (SPI0) +{ Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -365,6 +381,10 @@ Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) +} + +Scope (SPI1) +{ Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -416,6 +436,10 @@ Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) +} + +Scope (UAR0) +{ Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -467,6 +491,10 @@ Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) +} + +Scope (UAR1) +{ Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -505,6 +533,10 @@ Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) +} + +Scope (SDIO) +{ Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/38802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I086730102e68fd709e8d3bbcfa42855ff0a0ab99 Gerrit-Change-Number: 38802 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/intel/broadwell: Isolate _HID and _ADR
by Angel Pons (Code Review) 09 Feb '20

09 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38803 ) Change subject: [WIP] soc/intel/broadwell: Isolate _HID and _ADR ...................................................................... [WIP] soc/intel/broadwell: Isolate _HID and _ADR That way, newer IASL won't complain about it. Change-Id: I884e203dd6fac99b11d12a88b5f972587ddae4d9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi/serialio.asl 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/38803/1 diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..35eac5a 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -159,6 +159,10 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) +} + +Scope (SDMA) +{ Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -205,6 +209,10 @@ Return ("INT33C2") } Name (_UID, 1) +} + +Scope (I2C0) +{ Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) @@ -276,6 +284,10 @@ Return ("INT33C3") } Name (_UID, 1) +} + +Scope (I2C1) +{ Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) @@ -347,6 +359,10 @@ Return ("INT33C0") } Name (_UID, 1) +} + +Scope (SPI0) +{ Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -403,6 +419,10 @@ Return ("INT33C1") } Name (_UID, 1) +} + +Scope (SPI1) +{ Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -471,6 +491,10 @@ Return ("INT33C4") } Name (_UID, 1) +} + +Scope (UAR0) +{ Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -539,6 +563,10 @@ Return ("INT33C5") } Name (_UID, 1) +} + +Scope (UAR1) +{ Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -596,6 +624,10 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) +} + +Scope (SDIO) +{ Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/38803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I884e203dd6fac99b11d12a88b5f972587ddae4d9 Gerrit-Change-Number: 38803 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/stm: Add platform opt-in Kconfig
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Aaron Durbin, Arthur Heymans, cedarhouse1(a)comcast.net, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38764 to review the following change. Change subject: intel/stm: Add platform opt-in Kconfig ...................................................................... intel/stm: Add platform opt-in Kconfig Selecting STM on an arbitrary platform would likely result in a brick, so let's hide the prompt by default. Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/security/intel/stm/Kconfig M src/soc/intel/skylake/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38764/1 diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index a74eba8..144deed 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,9 +1,12 @@ +config PLATFORM_SUPPORTS_STM + bool + depends on SMM_TSEG config STM bool "Enable STM" default n - depends on SMM_TSEG + depends on PLATFORM_SUPPORTS_STM select USE_BLOBS help diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6277cea..ae60a63 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -44,6 +44,7 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR -- To view, visit https://review.coreboot.org/c/coreboot/+/38764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8 Gerrit-Change-Number: 38764 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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