coreboot-gerrit February 2020

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 11 Feb '20

11 Feb '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#63). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- -------------------- -------------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 + BP3 | DATA | ------------- -------------------- -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 505 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/63 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 63 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/amdfwtool: Add script to verify signature of PSP firmware file
by Marshall Dawson (Code Review) 11 Feb '20

11 Feb '20

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17363 ) Change subject: util/amdfwtool: Add script to verify signature of PSP firmware file ...................................................................... Patch Set 2: BTW when the PSP team sent me the starting file for CB:37847, I asked specifically whether they minded if I also published this too. Those guys are extraordinarily busy so it wasn't much surprise that they didn't bother to answer. I'll keep it in mind though and try to publish it sometime. -- To view, visit https://review.coreboot.org/c/coreboot/+/17363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3610235a6ca7989f2e3594ca036b6afce70f5fb0 Gerrit-Change-Number: 17363 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Feb 2020 02:54:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNING
by Subrata Banik (Code Review) 11 Feb '20

11 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38801 ) Change subject: Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNING ...................................................................... Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNING Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig symbol. Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38801/1 diff --git a/src/Kconfig b/src/Kconfig index 4253ec7..f75f942 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -369,9 +369,9 @@ config MINIMAL_PCI_SCANNING bool "Enable minimal PCI scanning" - depends on CONFIGURABLE_RAMSTAGE + depends on CONFIGURABLE_RAMSTAGE && PCI help - If this option is enabled, coreboot will scan only devices + If this option is enabled, coreboot will scan only PCI devices marked as mandatory in devicetree.cb endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/38801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c Gerrit-Change-Number: 38801 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Guard CONFIGURABLE_RAMSTAGE
by Subrata Banik (Code Review) 11 Feb '20

11 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38795 ) Change subject: Kconfig: Guard CONFIGURABLE_RAMSTAGE ...................................................................... Kconfig: Guard CONFIGURABLE_RAMSTAGE This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it. TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default. Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38795/1 diff --git a/src/Kconfig b/src/Kconfig index 3742c04..4253ec7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,9 +354,13 @@ Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI). +config HAVE_CONFIGURABLE_RAMSTAGE + bool + config CONFIGURABLE_RAMSTAGE bool "Enable a configurable ramstage." default y if ARCH_X86 + depends on HAVE_CONFIGURABLE_RAMSTAGE help A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step. -- To view, visit https://review.coreboot.org/c/coreboot/+/38795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Gerrit-Change-Number: 38795 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/tigerlake: Add asl support for USBC
by Shaunak Saha (Code Review) 10 Feb '20

10 Feb '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38439 ) Change subject: [WIP]soc/intel/tigerlake: Add asl support for USBC ...................................................................... Abandoned Abandoning this as John have a new patchset -- To view, visit https://review.coreboot.org/c/coreboot/+/38439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44fd726c14f96bd3c963f17ec8e0abc956a76ebd Gerrit-Change-Number: 38439 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGE
by Joel Kitching (Code Review) 10 Feb '20

10 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38778 ) Change subject: vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGE ...................................................................... vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGE Part of the design of vboot persistent context is that the workbuf gets placed in CBMEM and stays there for depthcharge to use in kernel verification. As such, the space allocated in CBMEM needs to be at least VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context() would get invoked for the first time after CBMEM comes up, and it would only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE. Initialize the workbuf directly in vboot_setup_cbmem() instead with the correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. BUG=b:124141368, chromium:994060 TEST=make clean && make test-abuild TEST=boot on a system with VBOOT_STARTS_IN_ROMSTAGE BRANCH=none Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/common.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38778/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index aeb4498..de3eba9 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -86,6 +86,7 @@ static void vboot_setup_cbmem(int unused) { + vb2_error_t rv; const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wb_cbmem != NULL); @@ -96,7 +97,16 @@ * from SRAM/CAR into CBMEM. */ if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - assert(vb2api_relocate(wb_cbmem, _vboot2_work, cbmem_size, - &vboot_ctx) == VB2_SUCCESS); + rv = vb2api_relocate(wb_cbmem, _vboot2_work, cbmem_size, + &vboot_ctx); + /* + * For platforms where VBOOT_STARTS_IN_ROMSTAGE, verification occurs + * after CBMEM is brought online. Directly initialize vboot data + * structures in CBMEM, which will also be available downstream. + */ + else + rv = vb2api_init(wb_cbmem, cbmem_size, &vboot_ctx); + + assert(rv == VB2_SUCCESS); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) -- To view, visit https://review.coreboot.org/c/coreboot/+/38778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a Gerrit-Change-Number: 38778 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth Mercury White (la...
by Jonathan Neuschäfer (Code Review) 10 Feb '20

10 Feb '20

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 ) Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019) ...................................................................... Patch Set 14: Code-Review+1 (2 comments) A few small comments https://review.coreboot.org/c/coreboot/+/37565/14/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_icl/board_info.txt: https://review.coreboot.org/c/coreboot/+/37565/14/src/mainboard/razer/blade… PS14, Line 2: Board name: Blade Stealth Ice Lake U Mercury White late 2019 (LY320) This is not the same as the name in Kconfig.name. Is this difference intended? https://review.coreboot.org/c/coreboot/+/37565/14/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_icl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37565/14/src/mainboard/razer/blade… PS14, Line 167: #+-------------------+---------------------------+ The table formatting is broken, here -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 14 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Mon, 10 Feb 2020 21:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/supermicro: x11ssm-f: disable SUART3/4
by Nico Huber (Code Review) 10 Feb '20

10 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38818 ) Change subject: mainboard/supermicro: x11ssm-f: disable SUART3/4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Gerrit-Change-Number: 38818 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Feb 2020 20:15:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4
by Nico Huber (Code Review) 10 Feb '20

10 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38817 ) Change subject: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Gerrit-Change-Number: 38817 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Mon, 10 Feb 2020 20:15:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4
by Patrick Rudolph (Code Review) 10 Feb '20

10 Feb '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38817 ) Change subject: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Gerrit-Change-Number: 38817 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Mon, 10 Feb 2020 20:12:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2020