Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38818 )
Change subject: mainboard/supermicro: x11ssm-f: disable SUART3/4
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mainboard/supermicro: x11ssm-f: disable SUART3/4
......................................................................
Patch Set 1:
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Change subject: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4
......................................................................
Patch Set 1:
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Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 )
Change subject: soc/intel/tigerlake: Add code for early tcss
......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e…
File src/soc/intel/tigerlake/early_tcss.c:
https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e…
PS28, Line 103: mux_data.dp_mode
> there is no ffs in coreboot that I'm aware of :(... […]
EC send this PIN mode in bitwise format but PMC needs it in natural number format.
you can use switch case and call out explicitly or use ffs()
http://man7.org/linux/man-pages/man3/ffs.3.html
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Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 )
Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37867/17/src/ec/google/chromeec/ec…
File src/ec/google/chromeec/ec_commands.h:
https://review.coreboot.org/c/coreboot/+/37867/17/src/ec/google/chromeec/ec…
PS17, Line 5252: uint8_t reserved; /* Reserved for future use */
> What's the purpose of this? If we need more information later, we can create a v3.
yes we can make V3 however as address is same and we are not using cable_type anymore we are making it reserved .
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 )
Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37867/17/src/ec/google/chromeec/ec…
File src/ec/google/chromeec/ec_commands.h:
https://review.coreboot.org/c/coreboot/+/37867/17/src/ec/google/chromeec/ec…
PS17, Line 5252: uint8_t reserved; /* Reserved for future use */
What's the purpose of this? If we need more information later, we can create a v3.
https://review.coreboot.org/c/coreboot/+/37867/17/src/ec/google/chromeec/ec…
PS17, Line 5537: USB_PD_CTRL_NONE
Wouldn't someone using this just check for !(flags & USB_PD_CTRL_USB_ENABLED) ?
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Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 )
Change subject: soc/intel/common/block: Enable PMC IPC driver
......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc…
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/37871/17/src/soc/intel/common/bloc…
PS17, Line 34: pmc_ipc_cmd
> As I think about this more, it might make sense to just have a union: […]
I was actually thinking the same thing...this never changes so might as well just make it a union here. I will add the information I have on how to use this
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Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 )
Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019)
......................................................................
Patch Set 14: Code-Review+1
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Hello Kyösti Mälkki, Christoph Pomaska, Angel Pons, Paul Menzel, Jonathan Neuschäfer, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37565
to look at the new patch set (#14).
Change subject: mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019)
......................................................................
mb/razer: Add initial support for the Blade Stealth Mercury White (late 2019)
The Razer Blade Stealth Mercury White is a Ice Lake system using:
- Intel i7-1065G7 (Ice Lake with Iris Plus GPU)
- ITE IT8320VG EC (currently unsupported in coreboot)
- Samsung M981 MZ-VLKB2560 256GB NVMe SSD
- Four Samsung K4UBE3D4AM-GHCL LPDDR4 chips
- Integrated TitanRidge Thunderbolt 3 / 4 controller
- Two Realtek Audio chips:
- ALC298 for the audio jack
- ALC1306 for the speakers
- Parade PS8802 USB Type-C Host Switch
- Unlabeled Intel USB Type-C Thunderbolt Switch
This commit includes basic ram init and devicetree configuration
and therefore everything required to call into the payload.
It is missing ACPI, power and advanced device initialization
as well as EC support which should be included on its own in
a future commit.
Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a
Signed-off-by: Johanna Schander <coreboot(a)mimoja.de>
---
A src/mainboard/razer/blade_stealth_icl/Kconfig
A src/mainboard/razer/blade_stealth_icl/Kconfig.name
A src/mainboard/razer/blade_stealth_icl/Makefile.inc
A src/mainboard/razer/blade_stealth_icl/acpi/mainboard.asl
A src/mainboard/razer/blade_stealth_icl/board_info.txt
A src/mainboard/razer/blade_stealth_icl/bootblock.c
A src/mainboard/razer/blade_stealth_icl/devicetree.cb
A src/mainboard/razer/blade_stealth_icl/dsdt.asl
A src/mainboard/razer/blade_stealth_icl/gpio.h
A src/mainboard/razer/blade_stealth_icl/hda_verb.c
A src/mainboard/razer/blade_stealth_icl/ramstage.c
A src/mainboard/razer/blade_stealth_icl/romstage.c
A src/mainboard/razer/blade_stealth_icl/spd/Makefile.inc
A src/mainboard/razer/blade_stealth_icl/spd/samsung_K4UBE3D4AA.spd.hex
14 files changed, 649 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37565/14
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