coreboot-gerrit February 2020

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Change in coreboot[master]: cpu/intel: Drop unused file
by HAOUAS Elyes (Code Review) 09 Feb '20

09 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37161 ) Change subject: cpu/intel: Drop unused file ...................................................................... cpu/intel: Drop unused file Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/cpu/intel/thermal_monitoring/thermal_monitoring.h 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37161/1 diff --git a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h b/src/cpu/intel/thermal_monitoring/thermal_monitoring.h deleted file mode 100644 index 5bb9cc2..0000000 --- a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THERMAL_MONITORING_OFF 0 -#define THERMAL_MONITORING_SET 0x00000008 -#define MISC_ENABLE 0x01a0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Gerrit-Change-Number: 37161 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t400: Configure panel-power sequencing
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Swift Geek (Sebastian Grzywna), Paul Menzel, Bill XIE, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38576 to review the following change. Change subject: mb/lenovo/t400: Configure panel-power sequencing ...................................................................... mb/lenovo/t400: Configure panel-power sequencing If the panel-power sequencer is not configured, libgfxinit falls back to very conservative defaults (210ms before EDID is probed). This results in a boot penalty of >100ms (depending on how long it takes to probe other ports). Values are taken from the VBTs already checked in. Untested. Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t400/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38576/1 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9561dfa..0eea193 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -3,6 +3,11 @@ register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms + register "gpu_panel_power_down_delay" = "250" # T3: 25ms + register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms + register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms + register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/38576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Gerrit-Change-Number: 38576 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t400: Correct display port list for R500 variant
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Swift Geek (Sebastian Grzywna), Paul Menzel, Bill XIE, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38574 to review the following change. Change subject: mb/lenovo/t400: Correct display port list for R500 variant ...................................................................... mb/lenovo/t400: Correct display port list for R500 variant The second digital display connector is unused, but strapped as if it were used. Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can ignore these. Based on schematics only, not tested. Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38574/1 diff --git a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads index 680dd1b..8a72a31 100644 --- a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads @@ -23,7 +23,6 @@ ports : constant Port_List := (DP1, HDMI1, - HDMI2, Analog, Internal, others => Disabled); -- To view, visit https://review.coreboot.org/c/coreboot/+/38574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Gerrit-Change-Number: 38574 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t400: Correct display port list for [TW]500 variants
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Swift Geek (Sebastian Grzywna), Paul Menzel, Bill XIE, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38573 to review the following change. Change subject: mb/lenovo/t400: Correct display port list for [TW]500 variants ...................................................................... mb/lenovo/t400: Correct display port list for [TW]500 variants T500 and W500 (Coronado-5) use both digital display connectors. Both with the DP AUX channel implemented, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/38573/1 diff --git a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads index 680dd1b..71d1600 100644 --- a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads @@ -23,6 +23,7 @@ ports : constant Port_List := (DP1, HDMI1, + DP2, HDMI2, Analog, Internal, -- To view, visit https://review.coreboot.org/c/coreboot/+/38573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Gerrit-Change-Number: 38573 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t400: Correct display port list for [RT]400 variants
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Swift Geek (Sebastian Grzywna), Paul Menzel, Bill XIE, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38572 to review the following change. Change subject: mb/lenovo/t400: Correct display port list for [RT]400 variants ...................................................................... mb/lenovo/t400: Correct display port list for [RT]400 variants The first digital display connector is unused, but strapped as if it were on later revisions. The DP AUX channel of the second connector is implemented, though, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38572/1 diff --git a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads index 680dd1b..92702b2 100644 --- a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads @@ -21,8 +21,7 @@ private package GMA.Mainboard is ports : constant Port_List := - (DP1, - HDMI1, + (DP2, HDMI2, Analog, Internal, -- To view, visit https://review.coreboot.org/c/coreboot/+/38572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Gerrit-Change-Number: 38572 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t400: Move `gma-mainboard.ads` to variants
by Nico Huber (Code Review) 09 Feb '20

09 Feb '20

Hello Kyösti Mälkki, Swift Geek (Sebastian Grzywna), Paul Menzel, Bill XIE, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38571 to review the following change. Change subject: mb/lenovo/t400: Move `gma-mainboard.ads` to variants ...................................................................... mb/lenovo/t400: Move `gma-mainboard.ads` to variants Some board revisions have the straps for display port detection configured wrong. So with a single list covering all variants' possible outputs, we make libgfxinit probe unimplemented ports which may stall the GMBUS controller and delay the boot for some hundred milliseconds. This just copies the list to the various variants with different display ports, so we can test the actual changes individually. Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t400/Makefile.inc R src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads C src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads C src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads 4 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/38571/1 diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index e4e6a1f..5d5669e 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -22,4 +22,10 @@ ramstage-y += cstates.c ramstage-y += blc.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) +ramstage-$(CONFIG_BOARD_LENOVO_T400) += variants/t400/malibu-3/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_R400) += variants/t400/malibu-3/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_T500) += variants/t400/coronado-5/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_W500) += variants/t400/coronado-5/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_R500) += variants/r500/gma-mainboard.ads +endif diff --git a/src/mainboard/lenovo/t400/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads similarity index 100% rename from src/mainboard/lenovo/t400/gma-mainboard.ads rename to src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads diff --git a/src/mainboard/lenovo/t400/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads similarity index 100% copy from src/mainboard/lenovo/t400/gma-mainboard.ads copy to src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads diff --git a/src/mainboard/lenovo/t400/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads similarity index 100% copy from src/mainboard/lenovo/t400/gma-mainboard.ads copy to src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads -- To view, visit https://review.coreboot.org/c/coreboot/+/38571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Gerrit-Change-Number: 38571 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Remove qemu aarch64 from project ideas
by Patrick Rudolph (Code Review) 09 Feb '20

09 Feb '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38533 ) Change subject: Documentation: Remove qemu aarch64 from project ideas ...................................................................... Documentation: Remove qemu aarch64 from project ideas Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38533/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 5bc4cac..90164a2 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -64,28 +64,6 @@ ### Mentors * Timothy Pearson <tpearson(a)raptorengineering.com> -## Support QEMU AArch64 -Having QEMU support for the architectures coreboot can boot helps with -some (limited) compatibility testing: While QEMU generally doesn't need -much hardware init, any CPU state changes in the boot flow will likely -be quite close to reality. - -That could be used as a baseline to ensure that changes to architecture -code doesn't entirely break these architectures - -### Requirements -* coreboot knowledge: Should know the general boot flow in coreboot. -* other knowledge: This will require knowing how the architecture - typically boots, to adapt the coreboot payload interface to be - appropriate and, for example, provide a device tree in the platform's - typical format. -* hardware requirements: since QEMU runs practically everywhere and - needs no recovery mechanism, these are suitable projects when no special - hardware is available. - -### Mentors -* Patrick Georgi <patrick(a)georgi.software> - ## Add Kernel Address Sanitizer functionality to coreboot The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector. The idea is to check every memory access (variables) for its validity -- To view, visit https://review.coreboot.org/c/coreboot/+/38533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b Gerrit-Change-Number: 38533 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode
by Piotr Kleinschmidt (Code Review) 09 Feb '20

09 Feb '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35891 ) Change subject: src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode ...................................................................... src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode The attempt to install pfSense ended up in a SATA driver error. Changing SATA mode from IDE to AHCI solved that issue. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/southbridge/amd/pi/hudson/sata.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35891/1 diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 08e967d..8e58390 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -32,6 +32,9 @@ #define UNLOCK_BIT (1<<0) #define SATA_CAPABILITIES_REG 0xFC #define CFG_CAP_SPM (1<<12) + #define SATA_REV_SUBCLASS_REG 0x08 + #define SUBCLASS_AHCI_MODE 0x60000 + #define SATA_PROGRAMIF_AHCI 0x100 volatile u32 *ahci_ptr = (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); @@ -45,6 +48,11 @@ /* set the SATA AHCI mode to allow port expanders */ *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + /* enable AHCI mode */ + temp = pci_read_config32(dev, SATA_REV_SUBCLASS_REG); + temp = (temp & 0xFF0070FF) | SUBCLASS_AHCI_MODE | SATA_PROGRAMIF_AHCI; + pci_write_config32(dev, SATA_REV_SUBCLASS_REG, temp); + /* lock the write-protect */ temp = pci_read_config32(dev, MISC_CONTROL_REG); temp &= ~UNLOCK_BIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/35891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Gerrit-Change-Number: 35891 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_r...
by Sridhar Siricilla (Code Review) 09 Feb '20

09 Feb '20

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37282 to review the following change. Change subject: soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready() ...................................................................... soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready() Below changes are done: 1. Rename set_host_ready() function to cse_set_host_ready() 2. Additional debug messages are added TEST=Build and Boot hatch board. Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37282/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index f81411a..46ad8ce 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -272,7 +272,7 @@ } /* Makes the host ready to communicate with CSE */ -void set_host_ready(void) +void cse_set_host_ready(void) { uint32_t csr; csr = read_host_csr(); @@ -286,10 +286,13 @@ { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + printk(BIOS_ERR, "HECI: Wait 15 secs for CSE to enter SEC_OVERRIDE mode!\n"); while (!check_cse_sec_override_mode()) { udelay(HECI_DELAY); - if (stopwatch_expired(&sw)) + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out!\n"); return 0; + } } return 1; @@ -545,7 +548,7 @@ if (wait_heci_ready()) { /* Device is back on its imaginary feet, clear reset */ - set_host_ready(); + cse_set_host_ready(); return 1; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 4c00006..3c00b87 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -112,7 +112,7 @@ /* Makes the host ready to communicate with CSE*/ -void set_host_ready(void); +void cse_set_host_ready(void); /* * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds. -- To view, visit https://review.coreboot.org/c/coreboot/+/37282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Gerrit-Change-Number: 37282 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/lick: Set TCC offset for lick
by Hash Hung (Code Review) 09 Feb '20

09 Feb '20

Hash Hung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38506 ) Change subject: mb/google/octopus/variants/lick: Set TCC offset for lick ...................................................................... mb/google/octopus/variants/lick: Set TCC offset for lick Change tcc offset from 0 to 15 degree celsius for lick. BUG=b:147198431 BRANCH=octopus TEST=Build, and verify test result by thermal team. Signed-off-by: Hash.Hung <hash1.hung(a)lcfc.corp-partner.google.com> Change-Id: Ife6b02321145837e05c82f979998466b83317f86 --- M src/mainboard/google/octopus/variants/lick/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38506/1 diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index 41d078e..3aa369e 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -52,6 +52,8 @@ #| I2C5 | Audio | #| I2C6 | Trackpad | #+-------------------+---------------------------+ + register "tcc_offset" = "15" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/38506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife6b02321145837e05c82f979998466b83317f86 Gerrit-Change-Number: 38506 Gerrit-PatchSet: 1 Gerrit-Owner: Hash Hung <hash1.hung(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020