Change in coreboot[master]: mb/google/dedede: Add initial configuration for serial IO ports
Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38775 )
Change subject: mb/google/dedede: Add initial configuration for serial IO ports ......................................................................
mb/google/dedede: Add initial configuration for serial IO ports
Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38775/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2..2a0b760 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,39 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H"
+ register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38775 )
Change subject: mb/google/dedede: Add initial configuration for serial IO ports ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38775 )
Change subject: mb/google/dedede: Add initial configuration for serial IO ports ......................................................................
mb/google/dedede: Add initial configuration for serial IO ports
Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Justin TerAvest teravest@chromium.org --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 33 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2..2a0b760 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,39 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H"
+ register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device
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Justin TerAvest (Code Review) -
Karthik Ramasubramanian (Code Review)
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Patrick Georgi (Code Review)