Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
mb/google/dedede: Add Compute & PCH Global device IDs
Add compute and PCH Global device IDs with the concerned devices turned off.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38738/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index eb9dc1c..cdd325c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -2,4 +2,50 @@ device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device pci 00.0 off end # Host Bridge + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 09.0 off end # Intel Trace Hub + device pci 12.6 off end # GSPI 2 + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 off end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 off end # eSPI Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + end end
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... PS1, Line 7: device pci 00.0 off end # Host Bridge Don’t we also use tabs for indentation? Please add a commit before this one to fix the existing block above.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... PS1, Line 7: device pci 00.0 off end # Host Bridge
Don’t we also use tabs for indentation? Please add a commit before this one to fix the existing bloc […]
The code is indented using tabs - both in the new one and the existing block. I am not sure if/where you are seeing differently.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38738/1/src/mainboard/google/dedede... PS1, Line 7: device pci 00.0 off end # Host Bridge
The code is indented using tabs - both in the new one and the existing block. […]
I looked at other devicetrees as well. Tabs are used at the start of the line for indentation. After that only spaces are used. Hence marking the comment as resolved. Please feel free to re-open the comment if I missed something.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38738 )
Change subject: mb/google/dedede: Add Compute & PCH Global device IDs ......................................................................
mb/google/dedede: Add Compute & PCH Global device IDs
Add compute and PCH Global device IDs with the concerned devices turned off.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Justin TerAvest teravest@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 46 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index eb9dc1c..cdd325c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -2,4 +2,50 @@ device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device pci 00.0 off end # Host Bridge + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 09.0 off end # Intel Trace Hub + device pci 12.6 off end # GSPI 2 + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 off end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 off end # eSPI Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + end end
-
Furquan Shaikh (Code Review) -
Justin TerAvest (Code Review)
-
Karthik Ramasubramanian (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)