coreboot-gerrit February 2020

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Change in coreboot[master]: soc/amd/common: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 08 Feb '20

08 Feb '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30512 ) Change subject: soc/amd/common: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: > Patch Set 4: > > You can abandon this.. Right. Thx. -- To view, visit https://review.coreboot.org/c/coreboot/+/30512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I394faaf2fd7795face19592ddc1bb23a67cac8a2 Gerrit-Change-Number: 30512 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Feb 2020 10:43:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel/apollolake: Add early smbus support
by Christian Gmeiner (Code Review) 08 Feb '20

08 Feb '20

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31461 Change subject: intel/apollolake: Add early smbus support ...................................................................... intel/apollolake: Add early smbus support Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/smbus.h 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31461/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..f7ddc6f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..99a9467 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,6 +23,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -112,6 +113,9 @@ /* Program TCO Timer Halt */ tco_configure(); + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); + /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..a4ff451 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -16,6 +16,9 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_RCV_SLVA 0x09 + /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) @@ -25,4 +28,7 @@ #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Gerrit-Change-Number: 31461 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Don't use CAR_GLOBAL
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30512 ) Change subject: soc/amd/common: Don't use CAR_GLOBAL ...................................................................... Patch Set 4: You can abandon this.. -- To view, visit https://review.coreboot.org/c/coreboot/+/30512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I394faaf2fd7795face19592ddc1bb23a67cac8a2 Gerrit-Change-Number: 30512 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 09:18:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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Change in coreboot[master]: intel/smm: Chain .pre_cpu_smm_trigger
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37144 ) Change subject: intel/smm: Chain .pre_cpu_smm_trigger ...................................................................... intel/smm: Chain .pre_cpu_smm_trigger Change-Id: I2533fc478441f5b790802df9a3ec63c5a2e496af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/em64t101.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/smm_reloc.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c 9 files changed, 65 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37144/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c4c34ca..eb0c22e 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -746,15 +746,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs @@ -775,7 +783,7 @@ void mp_init_cpus(struct bus *cpu_bus) { select_mp_ops_em64t101_cpu_save(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index ac9713f..f9e4827 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -300,15 +300,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs @@ -330,7 +338,7 @@ void mp_init_cpus(struct bus *cpu_bus) { select_mp_ops_em64t101(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index a5e66fe..a00757d 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -526,15 +526,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs diff --git a/src/cpu/intel/smm/em64t101.c b/src/cpu/intel/smm/em64t101.c index e4dd454..d3e45bc 100644 --- a/src/cpu/intel/smm/em64t101.c +++ b/src/cpu/intel/smm/em64t101.c @@ -54,7 +54,7 @@ * the saving state to each CPU's MSRs. At least one save state size * is required for the initial SMM entry for the BSP to determine if * parallel SMM relocation is even feasible. */ -void smm_relocate(void) +static void per_cpu_smm_trigger(void) { /* * If smm_save_state_in_msrs is non-zero then parallel SMM relocation @@ -68,12 +68,6 @@ smm_initiate_relocation(); } -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index eccd939..87ce02f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -33,12 +33,14 @@ #define SMRR_SUPPORTED (1 << 11) +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger_alt_1(void) { set_vmx_and_lock(); /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); } static void per_cpu_smm_trigger_alt_2(void) @@ -66,7 +68,7 @@ } /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); } /* The relocation work is actually performed in SMM context, but the code @@ -116,6 +118,7 @@ struct cpuinfo_x86 c; select_mp_ops_em64t101(mp_ops); + smm_trigger = mp_ops->per_cpu_smm_trigger; mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger_alt_1; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 790df30..64dda8d 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -54,9 +54,6 @@ void fill_in_ied_params(struct smm_relocation_params *params); void write_smm_msrs(int cpu, struct smm_relocation_params *relo_params); -/* These helpers are for performing SMM relocation. */ -void smm_relocate(void); - #define D_OPEN (1 << 6) #define D_CLS (1 << 5) #define D_LCK (1 << 4) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 44b3c59..28355bd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -138,17 +138,25 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { const struct pattrs *pattrs = pattrs_get(); /* Relocate SMM space. */ - smm_initiate_relocation(); + smm_trigger(); /* Load microcode after SMM relocation. */ intel_microcode_load_unlocked(pattrs->microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { smm_southbridge_enable_smi(); @@ -166,7 +174,7 @@ struct bus *cpu_bus = dev->link_list; select_mp_ops_em64t100(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7454f94..d803013 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,6 +147,8 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { const struct pattrs *pattrs = pattrs_get(); @@ -158,12 +160,18 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); /* Relocate SMM space. */ - smm_initiate_relocation(); + smm_trigger(); /* Load microcode after SMM relocation. */ intel_microcode_load_unlocked(pattrs->microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { smm_southbridge_enable_smi(); @@ -184,7 +192,7 @@ __FILE__, __func__, dev_name(dev)); select_mp_ops_em64t100(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index f19ee7a..6a514e9 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -635,15 +635,23 @@ *parallel = 1; } +static void (*smm_trigger)(void); + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_trigger(); /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); } +static void chain_smm_trigger(struct mp_ops *mp_ops) +{ + smm_trigger = mp_ops->per_cpu_smm_trigger; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -669,7 +677,7 @@ struct bus *cpu_bus = dev->link_list; select_mp_ops_em64t101_cpu_save(&mp_ops); - mp_ops.per_cpu_smm_trigger = per_cpu_smm_trigger; + chain_smm_trigger(&mp_ops); if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2533fc478441f5b790802df9a3ec63c5a2e496af Gerrit-Change-Number: 37144 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: [WIP] soc/intel: Refactor device ACPI names
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35736 ) Change subject: [WIP] soc/intel: Refactor device ACPI names ...................................................................... [WIP] soc/intel: Refactor device ACPI names Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/acpi.c 5 files changed, 21 insertions(+), 237 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35736/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 8e516f8..e53bb0c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -147,65 +147,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - /* DSDT: acpi/northbridge.asl */ - case SA_DEVFN_ROOT: - return "MCHC"; - /* DSDT: acpi/lpc.asl */ - case PCH_DEVFN_LPC: - return "LPCB"; - /* DSDT: acpi/xhci.asl */ - case PCH_DEVFN_XHCI: - return "XHCI"; - /* DSDT: acpi/pch_hda.asl */ - case PCH_DEVFN_HDA: - return "HDAS"; - /* DSDT: acpi/lpss.asl */ - case PCH_DEVFN_UART0: - return "URT1"; - case PCH_DEVFN_UART1: - return "URT2"; - case PCH_DEVFN_UART2: - return "URT3"; - case PCH_DEVFN_UART3: - return "URT4"; - case PCH_DEVFN_SPI0: - return "SPI1"; - case PCH_DEVFN_SPI1: - return "SPI2"; - case PCH_DEVFN_SPI2: - return "SPI3"; - case PCH_DEVFN_PWM: - return "PWM"; - case PCH_DEVFN_I2C0: - return "I2C0"; - case PCH_DEVFN_I2C1: - return "I2C1"; - case PCH_DEVFN_I2C2: - return "I2C2"; - case PCH_DEVFN_I2C3: - return "I2C3"; - case PCH_DEVFN_I2C4: - return "I2C4"; - case PCH_DEVFN_I2C5: - return "I2C5"; - case PCH_DEVFN_I2C6: - return "I2C6"; - case PCH_DEVFN_I2C7: - return "I2C7"; - /* Storage */ - case PCH_DEVFN_SDCARD: - return "SDCD"; - case PCH_DEVFN_EMMC: - return "EMMC"; - case PCH_DEVFN_SDIO: - return "SDIO"; - /* PCIe */ - case PCH_DEVFN_PCIE1: - return "RP03"; - case PCH_DEVFN_PCIE5: - return "RP01"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1a..1754964 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -74,66 +74,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 31dcc25..2ad5f52 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -280,10 +280,11 @@ #if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { - if (dev->path.pci.devfn == PCH_DEVFN_LPC) - return "LPC0"; - else - return NULL; +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif + return NULL; } #endif diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c..956f35f 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -37,67 +37,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 43f9c39..45756b3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -760,59 +760,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_CIO: return "ICIO"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDIO: return "SDIO"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Gerrit-Change-Number: 35736 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: util/sconfig: Emit array of PNP UART devices
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31934 ) Change subject: util/sconfig: Emit array of PNP UART devices ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/31934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9330bcd5545ec3f94c1c14ed4a639f1ef0548e43 Gerrit-Change-Number: 31934 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: [RFC] util/sconfig: Drop topology from early static tree
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31936 ) Change subject: [RFC] util/sconfig: Drop topology from early static tree ...................................................................... Abandoned Unable to resolve/remove cases of __SIMPLE_DEVICE__ and PCI polymorphic functions, with the amount of merged code that is not build-tested. Those are dependencies to using replacing early stages to use struct pointers for PCI devices. -- To view, visit https://review.coreboot.org/c/coreboot/+/31936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdc63123fb8bcb39a0fc86e1e60b8eebb909223c Gerrit-Change-Number: 31936 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Abandoned Due to the polymorphic PCI accessor functions and abused use of __SIMPLE_DEVICE__ and <soc/pci_devs.h> hiding things, it's not practical for me to do any work on this topic while there is huge amount of submitted source that is currently not build-tested and there is a longish patchtrain that would very likely need manual conflict resolutions to solve. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: [WIP] arch/x86: Remove explicit MMX enables
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27101 ) Change subject: [WIP] arch/x86: Remove explicit MMX enables ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a26ad4818c5ba744cac6a6f901f885c44270930 Gerrit-Change-Number: 27101 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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