coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Vijay P Hiremath (Code Review) 08 Feb '20

08 Feb '20

Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 29: (4 comments) https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 40: int req_size may be we can remove this variable in all 3 functions and use macro instead https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 103: mux_data.dp_mode ffs(mux_data.dp_mode); https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 125: r return here too for error in case of dp? https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 182: (uint8_t) remove -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 29 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 00:05:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has uploaded a new patch set (#29) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 265 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 29 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has uploaded a new patch set (#28) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- D 3rdparty/vboot M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 6 files changed, 265 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 28 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has uploaded a new patch set (#27) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M 3rdparty/vboot M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 6 files changed, 266 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 27 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Vijay P Hiremath (Code Review) 08 Feb '20

08 Feb '20

Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 26: (3 comments) https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 29: int req_size; cmd.ipc_cmd.len = directly assign macro and can remove this variable https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 32: cmd.ipc_cmd.subcmd = 0; these are not needed (all 3 commands), already initialized https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 86: tcss_req[1] |= (1 << 4); ? -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 26 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Fri, 07 Feb 2020 23:17:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
by Divya Sasidharan (Code Review) 08 Feb '20

08 Feb '20

Divya Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 ) Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/37867/13/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/13/src/ec/google/chromeec/ec… PS13, Line 1539: resp.reserve > Can you please point me to the corresponding EC CL for this? How does the EC know SoC port numbers? This is the CL: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1669880 -- To view, visit https://review.coreboot.org/c/coreboot/+/37867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00 Gerrit-Change-Number: 37867 Gerrit-PatchSet: 17 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 07 Feb 2020 23:16:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 ) Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) ...................................................................... Patch Set 17: (21 comments) https://review.coreboot.org/c/coreboot/+/37867/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37867/2//COMMIT_MSG@8 PS2, Line 8: > Please add more details, what the problem and the solution is. Done https://review.coreboot.org/c/coreboot/+/37867/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37867/5//COMMIT_MSG@7 PS5, Line 7: rc/ec/google/chromeec: Get Type-C Mux info from EC : : BUG=None : BRANCH=None : TEST= Tested boots from USB-TypeC flash drive : on TGLRVP > add more details in the commit msg Done https://review.coreboot.org/c/coreboot/+/37867/14//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37867/14//COMMIT_MSG@9 PS14, Line 9: EC being the TCPM decides the mux configuration : after negotiating with the port partner on the : Type-C port. The APIS added here will give the : current essential mux state information for a : given port. > Please reflow for 75 characters per line. Done https://review.coreboot.org/c/coreboot/+/37867/14//COMMIT_MSG@17 PS14, Line 17: USB-TypeC flash drive > Please give the model. Done https://review.coreboot.org/c/coreboot/+/37867/14//COMMIT_MSG@18 PS14, Line 18: on TGLRVP > Ditto. Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.h: https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 41: int > unit8_t Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 43: google_chromeec_usb_get_pd_ports > What about google_chromeec_get_num_pd_ports(int *num_ports) on line 321? Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 51: int > uint8_t Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.h File src/ec/google/chromeec/ec.h: https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 40: int google_chromeec_usb_get_pd_mux_info(int port); : int google_chromeec_usb_get_pd_ports(void); : uint8_t google_chromeec_pd_get_port_info(int port); : int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc); > Can you please add comments to these functions indicating what they do, what params they expect and […] Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.c File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 1417: #define PD_CC_DFP_ATTACHED 5 : #define PD_CC_DEBUG_ACC 6 : > Sure can add that. Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 1420: /** : * : */ > this is not good practice, either prefer to use comment section else don't keep this at all Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 1434: cmd.cmd_code = EC_CMD_USB_PD_CONTROL; : cmd.cmd_version = 3; : cmd.cmd_data_in = &pd_control; : cmd.cmd_size_in = sizeof(pd_control); : cmd.cmd_data_out = &resp; : cmd.cmd_size_out = sizeof(resp); : cmd.cmd_dev_index = 0; > Its a good idea. Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec.… PS2, Line 1521: cmd.cmd_code = EC_CMD_USB_PD_MUX_INFO; > nit: add line between 1520 and 1521 Done https://review.coreboot.org/c/coreboot/+/37867/11/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/11/src/ec/google/chromeec/ec… PS11, Line 1542: /** : * Check for the current mux state in EC : * Flags representing mux state : * USB_PD_MUX_USB_ENABLED BIT(0) : * USB_PD_MUX_DP_ENABLED BIT(1) : * USB_PD_MUX_POLARITY_INVERTED BIT(2) : * USB_PD_MUX_HPD_IRQ BIT(3) : * USB_PD_MUX_HPD_LVL BIT(4) : * USB_PD_MUX_SAFE_MODE BIT(5) : * : */ > I will remove this and say the flags can be found in ec_commands. […] Done https://review.coreboot.org/c/coreboot/+/37867/12/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/12/src/ec/google/chromeec/ec… PS12, Line 1485: int > uint8_t Done https://review.coreboot.org/c/coreboot/+/37867/12/src/ec/google/chromeec/ec… PS12, Line 1518: uint8_t google_chromeec_pd_get_port_info(int port) > how about? […] Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 1487: struct ec_params_usb_pd_control pd_control; : struct ec_response_usb_pd_control_v2 resp; : struct chromeec_command cmd; : : pd_control.port = port; : pd_control.role = USB_PD_CTRL_ROLE_NO_CHANGE; : pd_control.mux = USB_PD_CTRL_ROLE_NO_CHANGE; : pd_control.swap = USB_PD_CTRL_SWAP_NONE; : : cmd.cmd_code = EC_CMD_USB_PD_CONTROL; : cmd.cmd_version = 2; : cmd.cmd_data_in = &pd_control; : cmd.cmd_size_in = sizeof(pd_control); : cmd.cmd_data_out = &resp; : cmd.cmd_size_out = sizeof(resp); : cmd.cmd_dev_index = 0; > Please follow the style of struct initialization in this file. Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 1520: struct ec_params_locate_chip req; : struct ec_response_locate_chip resp; : struct chromeec_command cmd; : : req.type = EC_CHIP_TYPE_TCPC; : req.index = port; : : cmd.cmd_code = EC_CMD_LOCATE_CHIP; : cmd.cmd_version = 0; : cmd.cmd_data_in = &req; : cmd.cmd_size_in = sizeof(req); : cmd.cmd_data_out = &resp; : cmd.cmd_size_out = sizeof(resp); : cmd.cmd_dev_index = 0; : > Same here. Done https://review.coreboot.org/c/coreboot/+/37867/14/src/ec/google/chromeec/ec… PS14, Line 1549: struct chromeec_command cmd; : struct ec_response_usb_pd_mux_info resp_mux; : struct ec_params_usb_pd_mux_info req_mux; : : if (port < 0) : return -1; : : cmd.cmd_code = EC_CMD_USB_PD_MUX_INFO; : cmd.cmd_version = 0; : req_mux.port = port; : cmd.cmd_data_in = &req_mux; : cmd.cmd_size_in = sizeof(req_mux); : cmd.cmd_data_out = &resp_mux; : cmd.cmd_size_out = sizeof(resp_mux); : cmd.cmd_dev_index = 0; > Same here. Done https://review.coreboot.org/c/coreboot/+/37867/11/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/37867/11/src/ec/google/chromeec/ec… PS11, Line 5253: uint8_t control_flags; /* USB_PD_CTRL_*flags */ > The comment refers to USB_PD_CTRL* flags, but they are still called USB_PD_MUX* above. […] Done https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec_… File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/37867/2/src/ec/google/chromeec/ec_… PS2, Line 4993: } __ec_align1; > True. The new EC code base has inculcated this change. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00 Gerrit-Change-Number: 37867 Gerrit-PatchSet: 17 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 07 Feb 2020 23:14:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Comment-In-Reply-To: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Keith Short <keithshort(a)chromium.org> Comment-In-Reply-To: caveh jalali <caveh(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: trogdor: support mbn_version 6 with python build scripts
by mturney mturney (Code Review) 08 Feb '20

08 Feb '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35506 ) Change subject: trogdor: support mbn_version 6 with python build scripts ...................................................................... trogdor: support mbn_version 6 with python build scripts Developer/Reviewer, be aware of this patch from Mistral: https://review.coreboot.org/c/coreboot/+/33425/18 Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M util/qualcomm/createxbl.py M util/qualcomm/mbn_tools.py 2 files changed, 90 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35506/1 diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 4a21854..769e9f1e 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -44,6 +44,7 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ +# 05/21/19 rissha Added --mbn_version to add MBN header accordingly # 03/26/18 tv Added -e to enable extended MBNV5 support # 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature @@ -119,6 +120,10 @@ help="Removes ZI segments that have addresses greater" + \ " than 32 bits when converting from a 64 to 32 bit ELF") + parser.add_option("--mbn_version", + action="store", type="int", dest="mbn_version", + help="Add mbn header in elf image. '3', '5' or '6'") + (options, args) = parser.parse_args() if not options.elf_inp_file1: @@ -206,11 +211,16 @@ else: zi_oob_enabled = True + header_version = 3 + if options.elf_inp_xbl_sec: is_ext_mbn_v5 = True + header_version = 5 else: is_ext_mbn_v5 = False + if options.mbn_version: + header_version = options.mbn_version mbn_type = 'elf' header_format = 'reg' @@ -259,7 +269,7 @@ source_elf, target_hash, elf_out_file_name = target_phdr_elf, - secure_type = image_header_secflag) + secure_type = image_header_secflag, header_version = header_version ) if rv: raise RuntimeError, "Failed to run pboot_gen_elf" @@ -270,7 +280,8 @@ target_hash_hd, image_header_secflag, is_ext_mbn_v5, - elf_file_name = source_elf) + elf_file_name = source_elf, + header_version = header_version) if rv: raise RuntimeError, "Failed to create image header for hash segment" diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 12dc210..079e02e 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384 # 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and @@ -64,23 +65,24 @@ #---------------------------------------------------------------------------- # GLOBAL VARIABLES BEGIN #---------------------------------------------------------------------------- -PAD_BYTE_1 = 255 # Padding byte 1s -PAD_BYTE_0 = 0 # Padding byte 0s -SHA256_SIGNATURE_SIZE = 256 # Support SHA256 -MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates -MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type) -MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) -BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements -SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements -FLASH_PARTI_VERSION = 3 # Flash Partition Version Number -MAX_PHDR_COUNT = 100 # Maximum allowable program headers -CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root -VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON -MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE -MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature +PAD_BYTE_1 = 255 # Padding byte 1s +PAD_BYTE_0 = 0 # Padding byte 0s +SHA256_SIGNATURE_SIZE = 256 # Support SHA256 +MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates +MBN_HEADER_VERSION_3 = 3 # Mbn header_version 3 +MBN_HEADER_VERSION_5 = 5 # Mbn header_version 5 +MBN_HEADER_VERSION_6 = 6 # Mbn header_version 6 +MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) +BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements +SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements +MAX_PHDR_COUNT = 100 # Maximum allowable program headers +CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root +VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON +MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE +MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature -SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image -SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image +SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image +SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image # Magic numbers filled in for boot headers FLASH_CODE_WORD = 0x844BDCD1 @@ -528,7 +530,7 @@ class Boot_Hdr: def __init__(self, init_val): self.image_id = ImageType.NONE_IMG - self.flash_parti_ver = FLASH_PARTI_VERSION + self.flash_parti_ver = MBN_HEADER_VERSION_3 self.image_src = init_val self.image_dest_ptr = init_val self.image_size = init_val @@ -573,6 +575,10 @@ self.reserved_2, self.reserved_3 ] + if self.flash_parti_ver == MBN_HEADER_VERSION_6: + values.insert(10, self.metadata_size_qti) + values.insert(11, self.metadata_size) + if self.image_dest_ptr >= 0x100000000: values[3] = 0xFFFFFFFF @@ -584,8 +590,12 @@ # Write 10 entries(40B) or 20 entries(80B) of boot header if write_full_hdr is False: - s = struct.Struct('I'* 10) - values = values[:10] + if self.flash_parti_ver == MBN_HEADER_VERSION_6: + s = struct.Struct('I'* 12) + values = values[:12] + else: + s = struct.Struct('I'* 10) + values = values[:10] else: s = struct.Struct('I' * self.getLength()) @@ -912,7 +922,8 @@ write_full_hdr = False, in_code_size = None, cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, - num_of_pages = None): + num_of_pages = None, + header_version = None): # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): @@ -945,9 +956,12 @@ cert_chain_size = 0 image_size = code_size + if header_version: + assert header_version in [MBN_HEADER_VERSION_3, MBN_HEADER_VERSION_5, MBN_HEADER_VERSION_6], 'Not a valid MBN header version' + # For ELF or hashed images, image destination will be determined from an ELF input file if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf': - image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE + image_dest = get_hash_address(elf_file_name) + (header_size(header_version)) elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin': image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST'] image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE'] @@ -993,10 +1007,17 @@ boot_header.cert_chain_size = cert_chain_size if is_ext_mbn_v5 == True: - # If platform image integrity check is enabled - boot_header.flash_parti_ver = 5 # version - boot_header.image_src = 0 # sig_size_qc - boot_header.image_dest_ptr = 0 # cert_chain_size_qc + # If platform image integrity check is enabled + boot_header.flash_parti_ver = MBN_HEADER_VERSION_5 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + + if header_version == MBN_HEADER_VERSION_6: + boot_header.flash_parti_ver = MBN_HEADER_VERSION_6 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + boot_header.metadata_size_qti = 0 # qti_metadata size + boot_header.metadata_size = 0 # oem_metadata size # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: @@ -1021,9 +1042,20 @@ last_phys_addr = None, append_xml_hdr = False, is_sha256_algo = True, - cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE): + cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, + header_version = None): + sha_algo = 'SHA1' + if is_sha256_algo: + sha_algo = 'SHA256' + + if header_version == MBN_HEADER_VERSION_6: + sha_algo = 'SHA384' global MI_PROG_BOOT_DIGEST_SIZE - if (is_sha256_algo is True): + image_header_size = header_size(header_version) + + if (sha_algo == 'SHA384'): + MI_PROG_BOOT_DIGEST_SIZE = 48 + elif sha_algo == 'SHA256': MI_PROG_BOOT_DIGEST_SIZE = 32 else: MI_PROG_BOOT_DIGEST_SIZE = 20 @@ -1110,7 +1142,7 @@ fbuf = elf_in_fp.read(hash_size) if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: - hash = generate_hash(fbuf, is_sha256_algo) + hash = generate_hash(fbuf, sha_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1129,7 +1161,7 @@ file_buff = elf_in_fp.read(data_len) if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): - hash = generate_hash(file_buff, is_sha256_algo) + hash = generate_hash(file_buff, sha_algo) else: hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE @@ -1151,7 +1183,7 @@ # Initialize the hash table program header [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \ - initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64) + initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64) # Check if hash segment max size parameter was passed if (hash_seg_max_size is not None): @@ -1252,7 +1284,7 @@ # Read the program header and compute hash proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size) - hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo) + hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo) # Write hash to file as first hash table entry hash_out_fp.seek(0) @@ -1592,7 +1624,7 @@ page = page + elf_in_fp.read(bytes_in_page - len(page)) if (len(page) < DP_PAGE_SIZE): page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page))) - hashes = hashes + [generate_hash(page, True)] + hashes = hashes + [generate_hash(page, 'SHA256')] bytes_left -= bytes_in_page # And write them to the hash segment @@ -2101,9 +2133,20 @@ #---------------------------------------------------------------------------- # sha1/sha256 hash routine wrapper #---------------------------------------------------------------------------- -def generate_hash(in_buf, is_sha256_algo): +def header_size(header_version): + if header_version == MBN_HEADER_VERSION_6: + return 48 + else: + return 40 + +#---------------------------------------------------------------------------- +# sha1/sha256 hash routine wrapper +#---------------------------------------------------------------------------- +def generate_hash(in_buf, sha_algo): # Initialize a SHA1 object from the Python hash library - if (is_sha256_algo is True): + if sha_algo == 'SHA384': + m = hashlib.sha384() + elif sha_algo == 'SHA256': m = hashlib.sha256() else: m = hashlib.sha1() -- To view, visit https://review.coreboot.org/c/coreboot/+/35506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Gerrit-Change-Number: 35506 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 25: (13 comments) https://review.coreboot.org/c/coreboot/+/37870/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37870/10//COMMIT_MSG@10 PS10, Line 10: PMC IPC driver is needed to communicate with EC in order to : get status of the Type C ports > The example I mentioned is actually pre-kernel. It is still firmware. […] Ack https://review.coreboot.org/c/coreboot/+/37870/10//COMMIT_MSG@12 PS10, Line 12: > Can you please add relevant partner bug? Done https://review.coreboot.org/c/coreboot/+/37870/10/src/soc/intel/tigerlake/M… File src/soc/intel/tigerlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/37870/10/src/soc/intel/tigerlake/M… PS10, Line 33: $(CONFIG_TGL_CHROME_EC) > will change this to early_tcss config flag Done https://review.coreboot.org/c/coreboot/+/37870/10/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/10/src/soc/intel/tigerlake/e… PS10, Line 37: bool usb; : bool polarity; : bool ufp; : bool acc; : uint8_t usb3_port; : uint8_t usb2_port; > Can you please add comments indicating what these members really mean? Done https://review.coreboot.org/c/coreboot/+/37870/10/src/soc/intel/tigerlake/e… PS10, Line 78: int num_ports, i; > unsigned int Done https://review.coreboot.org/c/coreboot/+/37870/16/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/16/src/soc/intel/tigerlake/e… PS16, Line 155: mux_flags & USB_PD_MUX_USB_ENABLED > I assume all the flags only so usb, dp, cable, polarity, hpd_irq, and hpd_lvl? […] Done https://review.coreboot.org/c/coreboot/+/37870/17/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/17/src/soc/intel/tigerlake/e… PS17, Line 174: BS_DEV_ENABLE > ok I'll have to change this up a bit then and add an early_tcss.h file. […] Done https://review.coreboot.org/c/coreboot/+/37870/19/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/19/src/soc/intel/tigerlake/e… PS19, Line 71: /* send USB connect request */ : tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */ : mux_data.usb3_port << 4; : tcss_req[1] = mux_data.usb2_port | : mux_data.ufp << 4 | /* 1=UFP/0=DFP */ : mux_data.polarity << 5 | /* ORI-HSL */ : mux_data.polarity << 6 | /* ORI-SBU */ : mux_data.acc << 7; : req_size = 2; : printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" : "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); : > add a separate function, […] Done https://review.coreboot.org/c/coreboot/+/37870/22/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/22/src/soc/intel/tigerlake/e… PS22, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2020 Intel Corp. : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ > coreboot.org is switching to SPDX headers : […] Done https://review.coreboot.org/c/coreboot/+/37870/23/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/23/src/soc/intel/tigerlake/e… PS23, Line 123: tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */ : mux_data.usb3_port << 4; : tcss_req[1] = mux_data.usb2_port | : mux_data.ufp << 4 | /* 1=UFP/0=DFP */ : mux_data.polarity << 5 | /* ORI-HSL */ : mux_data.polarity << 6 | /* ORI-SBU */ : mux_data.acc << 7; : req_size = PMC_IPC_CONN_REQ_SIZE; : printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" : "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); : : /* Copy the request into the buffer */ : memcpy(wbuf, tcss_req, req_size); : : cmd.ipc_cmd.len = req_size; : > pls add a function, tcss_mux_connect() Ack https://review.coreboot.org/c/coreboot/+/37870/23/src/soc/intel/tigerlake/e… PS23, Line 145: ret = send_dp_required_ipc_commands(mux_data); > I was wondering about that one I will fix that Done https://review.coreboot.org/c/coreboot/+/37870/25/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/25/src/soc/intel/tigerlake/e… PS25, Line 49: printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" : "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); : : /* Copy the request into the buffer */ : memcpy(wbuf, tcss_req, req_size); : : return pmc_send_ipc_cmd(cmd.cmd, wbuf, rbuf); > req_size can be passed, […] Ack https://review.coreboot.org/c/coreboot/+/37870/25/src/soc/intel/tigerlake/e… PS25, Line 151: int mux_flags, dp_mode; > move to line 161, make uint8_t to keep consistent Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 25 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Fri, 07 Feb 2020 23:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020