coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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1797 discussions

Change in coreboot[master]: util/amdfwtool: Add script to verify signature of PSP firmware file
by Kyösti Mälkki (Code Review) 08 Feb '20

08 Feb '20

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/17363 ) Change subject: util/amdfwtool: Add script to verify signature of PSP firmware file ...................................................................... Abandoned Contains some NDA'd IP. -- To view, visit https://review.coreboot.org/c/coreboot/+/17363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3610235a6ca7989f2e3594ca036b6afce70f5fb0 Gerrit-Change-Number: 17363 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: x86/acpigen: Deprecat use of 'Processor()'
by HAOUAS Elyes (Code Review) 08 Feb '20

08 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37876 ) Change subject: x86/acpigen: Deprecat use of 'Processor()' ...................................................................... x86/acpigen: Deprecat use of 'Processor()' Processor() operator is deprecated, use Device() instead. Change-Id: Ic9ea2ed6a2128dc4fe94155d098c2a4f7c24d82f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpigen.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37876/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index cc724a0..d4536cf 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -332,6 +332,7 @@ acpigen_emit_namestring(name); } +/* Processor() is deprecated. Please use Device() instead */ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/37876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9ea2ed6a2128dc4fe94155d098c2a4f7c24d82f Gerrit-Change-Number: 37876 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: vendorcode/eltan/security: Switch to vb2 vboot library
by Wim Vervoorn (Code Review) 08 Feb '20

08 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38590 ) Change subject: vendorcode/eltan/security: Switch to vb2 vboot library ...................................................................... vendorcode/eltan/security: Switch to vb2 vboot library The eltan verified_boot is using the vboot 2.1 data structures and code, as well as the fwlib21 build target, they are all depreciated. Refer to CB:37654 for more information. The verified_boot code is updated to use the vb2 structures and code and make sure only public functions are used. BUG=N/A TEST=build Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/vendorcode/eltan/security/include/cb_sha.h M src/vendorcode/eltan/security/lib/Makefile.inc M src/vendorcode/eltan/security/lib/cb_sha.c M src/vendorcode/eltan/security/verified_boot/Kconfig M src/vendorcode/eltan/security/verified_boot/vboot_check.c 5 files changed, 69 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/38590/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h index 9a231d8..8b4e647 100644 --- a/src/vendorcode/eltan/security/include/cb_sha.h +++ b/src/vendorcode/eltan/security/include/cb_sha.h @@ -16,9 +16,8 @@ #ifndef __SECURITY_CB_SHA_H__ #define __SECURITY_CB_SHA_H__ -#include <2rsa.h> -#include <vb21_common.h> #include <vb2_api.h> +#include <vb2_sha.h> vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, uint8_t *digest); diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc index 2e11fb5..45a185a 100644 --- a/src/vendorcode/eltan/security/lib/Makefile.inc +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -16,7 +16,7 @@ # call with $1 = stage name to create rules for building the library # for the stage and adding it to the stage's set of object files. define vendor-security-lib -VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw21.a +VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw.a VEN_SEC_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\ $$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ $$(filter-out -I$(obj), $$(CPPFLAGS_$(1))))) @@ -32,29 +32,28 @@ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VEN_SEC_LIB_$(1)))) \ V=$(V) \ - fwlib21 + fwlib endef # vendor-security-for-stage CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include -CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) bootblock-y += cb_sha.c bootblock-y += ../../../../security/vboot/vboot_logic.c $(eval $(call vendor-security-lib,bootblock)) -bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a +bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw.a postcar-y += cb_sha.c $(eval $(call vendor-security-lib,postcar)) -postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw21.a +postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw.a ramstage-y += cb_sha.c $(eval $(call vendor-security-lib,ramstage)) -ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw21.a +ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw.a romstage-y += cb_sha.c $(eval $(call vendor-security-lib,romstage)) -romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw21.a +romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw.a -endif \ No newline at end of file +endif diff --git a/src/vendorcode/eltan/security/lib/cb_sha.c b/src/vendorcode/eltan/security/lib/cb_sha.c index 20a84af..b9777b7 100644 --- a/src/vendorcode/eltan/security/lib/cb_sha.c +++ b/src/vendorcode/eltan/security/lib/cb_sha.c @@ -20,11 +20,19 @@ { int i; int rv; - uint32_t digest_size = vb2_digest_size(hash_alg); + uint32_t digest_size; uint8_t result[VB2_MAX_DIGEST_SIZE]; - if (!digest_size) + switch (hash_alg) { + case VB2_HASH_SHA256: + digest_size = VB2_SHA256_DIGEST_SIZE; + break; + case VB2_HASH_SHA512: + digest_size = VB2_SHA512_DIGEST_SIZE; + break; + default: return VB2_ERROR_SHA_INIT_ALGORITHM; + } rv = vb2_digest_buffer(data, len, hash_alg, (uint8_t *)&result, digest_size); if (rv) diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index ab254c4..3f95bef 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -61,7 +61,6 @@ config VENDORCODE_ELTAN_VBOOT_KEY_SIZE int - default 610 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 - default 576 + default 552 endmenu # Verified Boot (verified_boot) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 461a847..ce7e99c 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -13,6 +13,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#define NEED_VB20_INTERNALS /* Peeking into vb2_shared_data */ + #include <boot_device.h> #include <bootmem.h> #include <cbfs.h> @@ -32,12 +35,17 @@ int verified_boot_check_manifest(void) { uint8_t *buffer; - uint8_t sig_buffer[1024]; /* used to build vb21_signature */ - size_t size = 0; - struct vb2_public_key key; - struct vb2_workbuf wb; - struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer; - uint8_t wb_buffer[1024]; + struct vb2_context *ctx; + struct vb2_kernel_preamble *pre; + static struct vb2_shared_data *sd; + size_t size; + uint8_t wb_buffer[2800]; + + if (vb2api_init(&wb_buffer, sizeof(wb_buffer), &ctx)) { + goto fail; + } + + sd = vb2_get_sd(ctx); buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); if (!buffer || !size) { @@ -46,48 +54,61 @@ } if ((size != CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) || - (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { + (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { printk(BIOS_ERR, "ERROR: Illegal public key!\n"); goto fail; } - if (vb21_unpack_key(&key, buffer, size)) { - printk(BIOS_ERR, "ERROR: Invalid public key!\n"); + /* + * Check if all items will fit into workbuffer: + * vb2_shared data, Public Key, Preamble data + */ + if ((sd->workbuf_used + size + sizeof(struct vb2_kernel_preamble) + + ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) > + sizeof(wb_buffer)) { + printk(BIOS_ERR, "ERROR: Work buffer too small\n"); goto fail; } + /* Add public key */ + sd->data_key_offset = sd->workbuf_used; + sd->data_key_size = size; + sd->workbuf_used += sd->data_key_size; + memcpy((void *)((void *)sd + (long)sd->data_key_offset), (uint8_t *)buffer, size); + + /* Fill preamble area */ + sd->preamble_size = sizeof(struct vb2_kernel_preamble); + sd->preamble_offset = sd->data_key_offset + sd->data_key_size; + sd->workbuf_used += sd->preamble_size; + pre = (struct vb2_kernel_preamble *)((void *)sd + (long)sd->preamble_offset); + + pre->flags = VB2_FIRMWARE_PREAMBLE_DISALLOW_HWCRYPTO; + + /* Fill body_signature (vb2_structure). RSA2048 key is used */ cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); - if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + - vb2_rsa_sig_size(VB2_SIG_RSA2048)) { + if (size != ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; } - - /* prepare work buffer structure */ - wb.buf = (uint8_t *)&wb_buffer; - wb.size = sizeof(wb_buffer); - - /* Build vb2_sig_hdr buffer */ - vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) + - (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE); - vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; - vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048); - vb2_sig_hdr->hash_alg = HASH_ALG; - vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; - memcpy(&sig_buffer[sizeof(struct vb21_signature)], + pre->body_signature.data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * + DIGEST_SIZE; + pre->body_signature.sig_offset = sizeof(struct vb2_signature) + + pre->body_signature.data_size; + pre->body_signature.sig_size = size - pre->body_signature.data_size; + sd->workbuf_used += size; + memcpy((void *)((void *)&pre->body_signature + (long)sizeof(struct vb2_signature)), (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); - if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size, - (struct vb21_signature *)&sig_buffer, &key, &wb)) { - printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n"); + + if (vb2api_verify_kernel_data(ctx, (void *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, + pre->body_signature.data_size)) goto fail; - } printk(BIOS_INFO, "%s: Successfully verified hash_table signature.\n", __func__); return 0; fail: - die("HASH table verification failed!\n"); + die("ERROR: HASH table verification failed!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318 Gerrit-Change-Number: 38590 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: mainboard/google/{hatch,fizz}: Fix gpio common code TODO
by Edward O'Callaghan (Code Review) 08 Feb '20

08 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38740 ) Change subject: mainboard/google/{hatch,fizz}: Fix gpio common code TODO ...................................................................... mainboard/google/{hatch,fizz}: Fix gpio common code TODO This is common gpio code that can come up in other cases as as well. See to fixing the TODO and not let it rot. BUG=b:147992492 BRANCH=none TEST=none Change-Id: I6c67f04ae458a0e47f4bb022d744dd8b8a0789ee Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/include/gpio.h M src/lib/gpio.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/puff/mainboard.c 4 files changed, 34 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38740/1 diff --git a/src/include/gpio.h b/src/include/gpio.h index 0a37ee7..3736f95 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -19,6 +19,8 @@ #include <soc/gpio.h> #include <types.h> +long wait_for_gpio(gpio_t gpio, long timeout); + /* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ _Static_assert(sizeof(gpio_t) <= sizeof(u32), "gpio_t doesn't fit in lb_gpio"); diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 8ea3b5e..578d583 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -16,6 +16,7 @@ #include <base3.h> #include <console/console.h> #include <delay.h> +#include <timer.h> #include <gpio.h> static void _check_num(const char *name, int num) @@ -179,6 +180,19 @@ return result; } +long wait_for_gpio(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + return -1; + } + mdelay(200); + } + return stopwatch_duration_msecs(&sw); +} + /* Default handler for ACPI path is to return NULL */ __weak const char *gpio_acpi_path(gpio_t gpio) { diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 9397786..527d5b2 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -238,27 +238,6 @@ #define GPIO_HDMI_HPD GPP_E13 #define GPIO_DP_HPD GPP_E14 -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - gpio_input(gpio); - - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - static void mainboard_chip_init(void *chip_info) { const struct pad_config *pads; @@ -270,8 +249,15 @@ gpio_input(GPIO_HDMI_HPD); if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + if (google_chromeec_wait_for_displayport(display_timeout_ms)) { + printk(BIOS_INFO, "Waiting for HPD\n"); + long t = wait_for_gpio(GPIO_DP_HPD, display_timeout_ms); + if (t >= 0) + printk(BIOS_INFO, "HPD ready after %lu ms\n", t); + else + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + } } pads = variant_gpio_table(&num); diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index 7354ce9..a245f6e 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -15,34 +15,13 @@ #include <baseboard/variants.h> #include <chip.h> -#include <delay.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> -#include <timer.h> #define GPIO_HDMI_HPD GPP_E13 #define GPIO_DP_HPD GPP_E14 -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; @@ -55,8 +34,15 @@ && !gpio_get(GPIO_HDMI_HPD) && !gpio_get(GPIO_DP_HPD)) { /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + if (google_chromeec_wait_for_displayport(display_timeout_ms)) { + printk(BIOS_INFO, "Waiting for HPD\n"); + long t = wait_for_gpio(GPIO_DP_HPD, display_timeout_ms); + if (t >= 0) + printk(BIOS_INFO, "HPD ready after %lu ms\n", t); + else + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c67f04ae458a0e47f4bb022d744dd8b8a0789ee Gerrit-Change-Number: 38740 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by caveh jalali (Code Review) 08 Feb '20

08 Feb '20

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 30: (5 comments) https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… PS30, Line 24: uint8_t cosnt... https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… PS30, Line 27: malloc do we really need to malloc 16 bytes? where's the free? https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… PS30, Line 27: wbuf we should probably zero out the buffer so we don't have unpredictable values getting copied into the unused portion of PMC_IPC_WBUF* https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… PS30, Line 39: 8 PMC_IPC_CONN_REQ_SIZE https://review.coreboot.org/c/coreboot/+/37870/30/src/soc/intel/tigerlake/e… PS30, Line 51: printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" : "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); : move all of these prints to send_ipc_command? -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 30 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 01:11:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 ) Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/37867/13/src/ec/google/chromeec/ec… File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/37867/13/src/ec/google/chromeec/ec… PS13, Line 1539: resp.reserve > This is the CL: https://chromium-review.googlesource. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00 Gerrit-Change-Number: 37867 Gerrit-PatchSet: 17 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 00:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 30: (8 comments) https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 29: int req_size; > cmd.ipc_cmd. […] Done https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 32: cmd.ipc_cmd.subcmd = 0; > I'd rather explicitly set the subcmd just to be sure. […] Done https://review.coreboot.org/c/coreboot/+/37870/26/src/soc/intel/tigerlake/e… PS26, Line 86: tcss_req[1] |= (1 << 4); > this should be a Macro... […] Done https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 40: int req_size > may be we can remove this variable in all 3 functions and use macro instead Done https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 103: mux_data.dp_mode > ffs(mux_data. […] there is no ffs in coreboot that I'm aware of :(...is it actually needed here? I'm not sure it is https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 125: r > return here too for error in case of dp? Done https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 172: dp_mode > &mux_data.dp_mode […] Done https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 182: (uint8_t) > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 30 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 00:37:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Comment-In-Reply-To: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 08 Feb '20

08 Feb '20

Brandon Breitenstein has uploaded a new patch set (#30) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 263 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 30 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: TEMP: sc7180: clock: Fix QUP DFSR configuration for perf levels
by mturney mturney (Code Review) 08 Feb '20

08 Feb '20

Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38389 to review the following change. Change subject: TEMP: sc7180: clock: Fix QUP DFSR configuration for perf levels ...................................................................... TEMP: sc7180: clock: Fix QUP DFSR configuration for perf levels Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 2 files changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/38389/1 diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b447a54..213c37f 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -72,7 +72,7 @@ .div = DIV(1), .m = 8, .n = 75, - .d_2 = 150, + .d_2 = 75, }, { .hz = 48 * MHz, @@ -80,7 +80,7 @@ .div = DIV(1), .m = 4, .n = 25, - .d_2 = 50, + .d_2 = 25, }, { .hz = 64 * MHz, @@ -88,7 +88,7 @@ .div = DIV(1), .m = 16, .n = 75, - .d_2 = 150, + .d_2 = 75, }, { .hz = 96 * MHz, @@ -96,7 +96,7 @@ .div = DIV(1), .m = 8, .n = 25, - .d_2 = 50, + .d_2 = 25, }, { .hz = 100 * MHz, @@ -236,7 +236,9 @@ struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - setbits32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT)); + clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, + BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), + BIT(CLK_CTL_CMD_DFSR_SHFT)); for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | @@ -247,7 +249,7 @@ if (qup_wrap_cfg[idx].m == 0) continue; - setbits32(&qup_clk->dfsr_clk.cmd_dfsr, + setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2e44b60..383e6d7 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -187,6 +187,7 @@ enum clk_ctl_dfsr { CLK_CTL_CMD_DFSR_BMSK = 0x1, CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, }; enum clk_qup { -- To view, visit https://review.coreboot.org/c/coreboot/+/38389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Gerrit-Change-Number: 38389 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Vijay P Hiremath (Code Review) 08 Feb '20

08 Feb '20

Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 29: (1 comment) https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/37870/28/src/soc/intel/tigerlake/e… PS28, Line 172: dp_mode &mux_data.dp_mode remove dp_mode -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 29 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Comment-Date: Sat, 08 Feb 2020 00:18:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020