Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46531 )
Change subject: util/sconfig: allow to override chip-wrapped devices
......................................................................
Patch Set 5: Code-Review+1
Tested with CB:46315 and worked on clevo/l140cu
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45952
to look at the new patch set (#21).
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
Currently, the ACPI PM timer state gets set in devicetree by the option
PmTimerDisabled. However, it is not board design dependent. Thus, add a
user-selectable Kconfig option.
Also, make the TCO SMI option select ACPI PM timer, since TCO won't work
without it.
The Kconfig option depends on CTC (Common Timer Copy), which a SoC has
to support to do PM ACPI timer emulation.
This new Kconfig gets used in the follow-up commits of this series.
Note: On Apollolake USE_PM_ACPI_TIMER gets selected statically to avoid
confusing the user in menuconfig, where the option is shown due to use
of the common code for PM Timer emulation. On APL there is not hardware
PM ACPI Timer, so emulation needs to be always enabled.
Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/smm/Kconfig
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/21
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Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45951
to look at the new patch set (#19).
Change subject: soc/intel: deduplicate ACPI timer emulation
......................................................................
soc/intel: deduplicate ACPI timer emulation
The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.
APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.
TODO: test this patch on APL hardware to prove this assumption ^
Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.
Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/common/block/cpu/Makefile.inc
A src/soc/intel/common/block/cpu/pm_timer_emulation.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/icelake/cpu.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/tigerlake/cpu.c
13 files changed, 36 insertions(+), 167 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/19
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Hello build bot (Jenkins), Nico Huber, Paul Menzel, Angel Pons, Subrata Banik, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46017
to look at the new patch set (#9).
Change subject: soc/intel/common: add Kconfig for PM Timer emulation support
......................................................................
soc/intel/common: add Kconfig for PM Timer emulation support
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.
This Kconfig gets used in the follow-up changes.
Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
9 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46017/9
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46531 )
Change subject: util/sconfig: allow to override chip-wrapped devices
......................................................................
Patch Set 5:
This change is ready for review.
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46274
to look at the new patch set (#16).
Change subject: {cpu,soc}/intel: deduplicate cpu code
......................................................................
{cpu,soc}/intel: deduplicate cpu code
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl,
tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common.
Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/include/cpu/intel/msr.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/cpu.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/tigerlake/cpu.c
15 files changed, 57 insertions(+), 412 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46274/16
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, David Guckian, Paul Menzel, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46278
to look at the new patch set (#11).
Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
......................................................................
{cpu,soc}/intel: replace AES-NI locking by common implemenation call
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.
Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/include/cpu/intel/msr.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/skylake/cpu.c
9 files changed, 12 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46278/11
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 )
Change subject: soc/intel: deduplicate ACPI timer emulation
......................................................................
Patch Set 18:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45951/15//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45951/15//COMMIT_MSG@9
PS15, Line 9: socs
: above
> Well, I wanted to be very specific here, because it may differ for some others (I have not checked x […]
Done
https://review.coreboot.org/c/coreboot/+/45951/18//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45951/18//COMMIT_MSG@10
PS18, Line 10: APL
> Please mention APL differences
Done
https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/…
File src/soc/intel/apollolake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/…
PS17, Line 13: ../../soc/intel/
> > > err, why is it done in the bootblock? We might want to move it later. […]
Nico checked this; APL does not have an ACPI timer in hardware; since ACPI timer is used in FSP-M, emulation needs to be enabled in bootblock
https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/common/bloc…
File src/soc/intel/common/block/cpu/pm_timer_emulation.c:
https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/common/bloc…
PS17, Line 26: msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
> Furquan, could you have a look at your docs, please, if APL needs that or has that setting at all?
APL does not have the delay registers; they seem to be writable, though. Nico assumed the could be dontcare -> needs test (added to commit message)
https://review.coreboot.org/c/coreboot/+/45951/18/src/soc/intel/common/bloc…
File src/soc/intel/common/block/include/intelblocks/cpulib.h:
https://review.coreboot.org/c/coreboot/+/45951/18/src/soc/intel/common/bloc…
PS18, Line 159: /* Enable the emulated ACPI timer to allow disabling the PM ACPI timer (PM1_TMR) */
> or in case it's not available (or just skip the reasoning, realize that what […]
Done
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, David Guckian, Paul Menzel, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46278
to look at the new patch set (#10).
Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
......................................................................
{cpu,soc}/intel: replace AES-NI locking by common implemenation call
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.
For model_2065x and model_206ax locking was moved from SMM to core init
because the MSR is core-scoped, not package-scoped.
Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/include/cpu/intel/msr.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/skylake/cpu.c
9 files changed, 12 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46278/10
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