coreboot-gerrit October 2020

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Change in coreboot[master]: AGESA mb: Replace tab with space in macro definition for consistency
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46518 ) Change subject: AGESA mb: Replace tab with space in macro definition for consistency ...................................................................... AGESA mb: Replace tab with space in macro definition for consistency With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/olivehill/buildOpts.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/asrock/imb-a180/buildOpts.c M src/mainboard/asus/a88xm-e/buildOpts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/biostar/a68n_5200/buildOpts.c M src/mainboard/biostar/am1ml/buildOpts.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/msi/ms7721/buildOpts.c 13 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46518/1 diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 0e09739..7a1f359 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 5ab39a1..0306346 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 433a9f4..72390c0 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index d7558f0..f5c2181 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c index 76fafca..25e7d3a 100644 --- a/src/mainboard/asus/a88xm-e/buildOpts.c +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -26,7 +26,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 6b57711..8600c27 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index d7558f0..f5c2181 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index d7558f0..f5c2181 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 461561d..808bace 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -11,7 +11,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE //#define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index d7558f0..f5c2181 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3aad89c..a3553c0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c0a87dd..19add3a 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 5740382..3a0ac1c 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -- To view, visit https://review.coreboot.org/c/coreboot/+/46518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Gerrit-Change-Number: 46518 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/Kconfig: Add missing dot in AMD domain www.amd.com
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46517 ) Change subject: vc/amd/Kconfig: Add missing dot in AMD domain www.amd.com ...................................................................... vc/amd/Kconfig: Add missing dot in AMD domain www.amd.com Fixes: b266c6b5 ("AMD Steppe Eagle: Add binary PI vendorcode files") Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/vendorcode/amd/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46517/1 diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index e080170..c7f48ac 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -20,7 +20,7 @@ Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group - (http://www.amdcom/embedded). + (http://www.amd.com/embedded). config CPU_AMD_AGESA_OPENSOURCE bool "open-source AGESA" -- To view, visit https://review.coreboot.org/c/coreboot/+/46517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Gerrit-Change-Number: 46517 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton/nct6779d: Add symbol to select COM port
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45971 ) Change subject: superio/nuvoton/nct6779d: Add symbol to select COM port ...................................................................... superio/nuvoton/nct6779d: Add symbol to select COM port Like the NCT6776 and NCT6791D, the NCT6779D has muxed COMA/GPIO8 functions. Since it requires setting different bits, add a new Kconfig symbol to do it. TEST=Selecting the symbol gives working serial console on the Asus F2A85-M PRO. Change-Id: I024ea86634b489985112ddb7ce07886e412e4c0b Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/nct6779d/Kconfig 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45971/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index cc21f40..6809a2a 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -53,7 +53,8 @@ nuvoton_pnp_enter_conf_state(dev); if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || - CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) + CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A) || + CONFIG(SUPERIO_NUVOTON_NCT6779D_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x40); diff --git a/src/superio/nuvoton/nct6779d/Kconfig b/src/superio/nuvoton/nct6779d/Kconfig index ce2af16..2427bdd 100644 --- a/src/superio/nuvoton/nct6779d/Kconfig +++ b/src/superio/nuvoton/nct6779d/Kconfig @@ -3,3 +3,8 @@ config SUPERIO_NUVOTON_NCT6779D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT6779D_COM_A + bool + depends on SUPERIO_NUVOTON_NCT6779D + default n -- To view, visit https://review.coreboot.org/c/coreboot/+/45971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024ea86634b489985112ddb7ce07886e412e4c0b Gerrit-Change-Number: 45971 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton: Only set bit 7 of global CR 0x2a for COM A
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46286 ) Change subject: superio/nuvoton: Only set bit 7 of global CR 0x2a for COM A ...................................................................... superio/nuvoton: Only set bit 7 of global CR 0x2a for COM A Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/superio/nuvoton/common/early_serial.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46286/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index cc21f40..f0b49c5 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -55,7 +55,7 @@ if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x40); + pnp_unset_and_set_config(dev, 0x2a, (1 << 7), 0); if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A)) /* Route COM A to GPIO8 pin group */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Gerrit-Change-Number: 46286 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: rework AES-NI locking
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 ) Change subject: cpu/intel/common: rework AES-NI locking ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46275/7/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46275/7/src/cpu/intel/common/commo… PS7, Line 281: /* Check if already locked */ > Isn't that literally repeating the code? It's exactly the kind of comment […] ack, since it's now pretty clear what the code does -- To view, visit https://review.coreboot.org/c/coreboot/+/46275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Gerrit-Change-Number: 46275 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 17 Oct 2020 13:32:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/46272/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46272/9//COMMIT_MSG@9 PS9, Line 9: Copy the AES-NI locking function to common cpu code to be able to reuse it. : : This change only copies the code and adds the MSR header file. Any further > Please break at 72 chars ack -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 13:31:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46278 ) Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/46278/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46278/9//COMMIT_MSG@13 PS9, Line 13: because the MSR is core-scoped, not package-scoped. > Please move this into a separate commit with "Fix" or something like […] ack -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 13:30:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/common: only lock AES-NI when supported
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46276 ) Change subject: cpu/intel/common: only lock AES-NI when supported ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46276/7/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46276/7/src/cpu/intel/common/commo… PS7, Line 277: /* Lock AES-NI only if supported */ > The code is very expressive now, is the comment still useful? oh not really, will drop that one -- To view, visit https://review.coreboot.org/c/coreboot/+/46276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Gerrit-Change-Number: 46276 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 17 Oct 2020 13:29:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… File src/soc/intel/icelake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX); > Your first ("is locked only if [...] VmxEnable=1") and last comment disagree. […] Yes exactly, unfortunately the first was wrong, because for some reason I saw a return where none is. iow FSP does everything and we can't change it if SkipMpInit is unavailable. -> I'd set VmxEnable = VMX_ENABLE and select FC lock statically for now -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 17 Oct 2020 13:22:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/txt: Add `txt_get_chipset_dpr` function
by Angel Pons (Code Review) 17 Oct '20

17 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46490 ) Change subject: intel/txt: Add `txt_get_chipset_dpr` function ...................................................................... intel/txt: Add `txt_get_chipset_dpr` function Due to platform-specific constraints, it is not possible to enable DPR by programming the MCH's DPR register in ramstage. Instead, assume it has been programmed earlier and check that its value is valid. If it is, then simply configure DPR in TXT public base with the same parameters. Note that some bits only exist on MCH DPR, and thus need to be cleared. Implement this function on most client platforms. For Skylake and newer, place it in common System Agent code. Also implement it for Haswell, for which the rest of Intel TXT support will be added in subsequent commits. Do not error out if DPR is larger than expected. On some platforms, such as Haswell, MRC decides the size of DPR, and cannot be changed easily. Reimplementing MRC is easier than working around its limitations anyway. Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.c M src/security/intel/txt/ramstage.c A src/security/intel/txt/txt_platform.h M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 60 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46490/1 diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index ac36e25..02d120b 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -9,6 +9,7 @@ #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt_register.h> #include "haswell.h" @@ -23,6 +24,11 @@ return CONFIG_SMM_TSEG_SIZE; } +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; +} + /* * Return the topmost memory address below 4 GiB available for general * use, from software's view of memory. Do not confuse this with TOLUD, @@ -39,9 +45,7 @@ */ uintptr_t tolum = northbridge_get_tseg_base(); - const union dpr_register dpr = { - .raw = pci_read_config32(HOST_BRIDGE, DPR), - }; + const union dpr_register dpr = txt_get_chipset_dpr(); /* Subtract DMA Protected Range size if enabled */ if (dpr.epm) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 263bc9d..f532a2f 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -13,6 +13,7 @@ #include <types.h> #include "txt.h" +#include "txt_platform.h" #include "txt_register.h" #include "txt_getsec.h" @@ -233,16 +234,42 @@ printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); if (dpr_capable) { - /* Protect 3 MiB below TSEG and lock register */ - union dpr_register dpr = { - .lock = 1, - .size = 3, - .top = tseg_base / MiB, - }; - write64((void *)TXT_DPR, dpr.raw); + /* Verify the DPR settings on the MCH and mirror them to TXT public space */ + union dpr_register dpr = txt_get_chipset_dpr(); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n", + (dpr.top - dpr.size) * MiB, dpr.size); // DPR TODO: implement SA_ENABLE_DPR in the intelblocks + if (!dpr.lock) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n"); + return; + } + + if (!dpr.epm || !dpr.prs) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n"); + return; + } + + if (dpr.size < 3) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); + return; + } + + if (dpr.top * MiB != tseg_base) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n"); + return; + } + + /* Clear reserved bits */ + dpr.prs = 0; + dpr.epm = 0; + + write64((void *)TXT_DPR, dpr.raw); + printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", read32((void *)TXT_DPR)); } diff --git a/src/security/intel/txt/txt_platform.h b/src/security/intel/txt/txt_platform.h new file mode 100644 index 0000000..8881cab --- /dev/null +++ b/src/security/intel/txt/txt_platform.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SECURITY_INTEL_TXT_PLATFORM_H__ +#define __SECURITY_INTEL_TXT_PLATFORM_H__ + +#include <types.h> +#include "txt_register.h" + +/* Prototypes to be defined in chipset code */ +union dpr_register txt_get_chipset_dpr(void); + +#endif /* __SECURITY_INTEL_TXT_PLATFORM_H__ */ diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index ffb6404..53d6077 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -7,6 +7,8 @@ #include <device/device.h> #include <device/pci.h> #include <intelblocks/systemagent.h> +#include <security/intel/txt/txt_platform.h> +#include <security/intel/txt/txt_register.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> @@ -145,3 +147,8 @@ { return sa_get_gsm_base() - sa_get_tseg_base(); } + +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(SA_DEV_ROOT, DPR) }; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Gerrit-Change-Number: 46490 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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