coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skylake: Do not let FSP set the subsystem IDs
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45006 ) Change subject: soc/intel/skylake: Do not let FSP set the subsystem IDs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Gerrit-Change-Number: 45006 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 16 Oct 2020 22:08:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: x86: Add some more CPUID helpers
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46285 ) Change subject: x86: Add some more CPUID helpers ...................................................................... x86: Add some more CPUID helpers Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/include/x86/arch/cpuid.h 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46285/1 diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index 8373301..c77be9c 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -32,4 +32,36 @@ #define cpuid(fn, eax, ebx, ecx, edx) \ asm("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "0"(fn)) +#define _declare_cpuid(reg) \ + static inline unsigned int cpuid_##reg(unsigned int fn) \ + { \ + unsigned int eax, ebx, ecx, edx; \ + cpuid(fn, eax, ebx, ecx, edx); \ + return reg; \ + } + +_declare_cpuid(eax) +_declare_cpuid(ebx) +_declare_cpuid(ecx) +_declare_cpuid(edx) + +#undef _declare_cpuid + +static inline unsigned int cpuid_max(void) +{ + return cpuid_eax(0); +} + +static inline unsigned int cpuid_family(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xff00000) >> (20 - 4) | (eax & 0xf00) >> 8; +} + +static inline unsigned int cpuid_model(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; +} + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Gerrit-Change-Number: 46285 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... soc/intel/skylake: Rename PcieRpAspm devicetree config This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/facebook/monolith/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 95e2565..bb11d06 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -151,7 +151,7 @@ # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[2]" = "1" # Disable Aspm - register "PcieRpAspm[2]" = "AspmDisabled" + register "pcie_rp_aspm[2]" = "AspmDisabled" # PCIE Port 4 disabled # PCIE Port 5 x1 -> MODULE i219 @@ -166,7 +166,7 @@ # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Disable Aspm - register "PcieRpAspm[5]" = "AspmDisabled" + register "pcie_rp_aspm[5]" = "AspmDisabled" # PCIE Port 7 Disabled # PCIE Port 8 Disabled @@ -184,7 +184,7 @@ # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[8]" = "1" # Disable Aspm - register "PcieRpAspm[8]" = "AspmDisabled" + register "pcie_rp_aspm[8]" = "AspmDisabled" # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4139570..549f403 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -210,8 +210,8 @@ sizeof(params->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; - if (config->PcieRpAspm[i]) - params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_aspm[i]) + params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1; if (config->pcie_rp_l1substates[i]) params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5befb01..2584d5d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -262,7 +262,7 @@ AspmL1, AspmL0sL1, AspmAutoConfig, - } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 22:03:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… File src/soc/intel/icelake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX); > Ouch, now I know where the problem is... 2) is impossible with SkipMpInit=0. […] Your first ("is locked only if [...] VmxEnable=1") and last comment disagree. Please confirm. -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 16 Oct 2020 21:21:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel,soc/intel: drop Kconfig for hyperthreading
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46507 ) Change subject: cpu/intel,soc/intel: drop Kconfig for hyperthreading ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Gerrit-Change-Number: 46507 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 21:08:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[refs/meta/config]: Do not copy Jenkins scores on rebase
by Angel Pons (Code Review) 16 Oct '20

16 Oct '20

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42744 ) Change subject: Do not copy Jenkins scores on rebase ...................................................................... Abandoned Makes no practical difference. -- To view, visit https://review.coreboot.org/c/coreboot/+/42744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: refs/meta/config Gerrit-Change-Id: Ic37406b95e997a202972cf3813122e91cc1a2f9b Gerrit-Change-Number: 42744 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[refs/meta/config]: Do not copy Jenkins scores on rebase
by Angel Pons (Code Review) 16 Oct '20

16 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42744 ) Change subject: Do not copy Jenkins scores on rebase ...................................................................... Patch Set 6: > Patch Set 6: Code-Review+2 > > I don't really care either way: our current cherry-pick strategy does the same and has no approving test-build slipped in, either (and gerrit provides no facility to do that), so the current behavior isn't really a regression. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: refs/meta/config Gerrit-Change-Id: Ic37406b95e997a202972cf3813122e91cc1a2f9b Gerrit-Change-Number: 42744 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 20:57:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: correct indentation
by Tim Wawrzynczak (Code Review) 16 Oct '20

16 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46467 ) Change subject: soc/intel/common/acpi: correct indentation ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Gerrit-Change-Number: 46467 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 20:53:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: rework AES-NI locking
by Tim Wawrzynczak (Code Review) 16 Oct '20

16 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 ) Change subject: cpu/intel/common: rework AES-NI locking ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Gerrit-Change-Number: 46275 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 16 Oct 2020 20:40:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020