coreboot-gerrit October 2020

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Change in coreboot[master]: acpi/acpigen_dsm: fix I2C HID DSM to report correct function support
by Josie Nordrum (Code Review) 16 Oct '20

16 Oct '20

Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46429 ) Change subject: acpi/acpigen_dsm: fix I2C HID DSM to report correct function support ...................................................................... acpi/acpigen_dsm: fix I2C HID DSM to report correct function support Fix DSM function 0 (query function) to correctly report function support for its revision. Revision 1 should return 0x3, all higher revisions should return 0. BUG=b:170862147 BRANCH=Zork TEST=check for dmesg error Signed-off-by: Josie Nordrum <JosieNordrum(a)google.com> Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56 --- M src/acpi/acpigen_dsm.c 1 file changed, 3 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46429/1 diff --git a/src/acpi/acpigen_dsm.c b/src/acpi/acpigen_dsm.c index 2336537..6a89c73 100644 --- a/src/acpi/acpigen_dsm.c +++ b/src/acpi/acpigen_dsm.c @@ -12,23 +12,15 @@ /* ToInteger (Arg1, Local2) */ acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); /* If (LEqual (Local2, 0x0)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x0); - /* Return (Buffer (One) { 0x1f }) */ - acpigen_write_return_singleton_buffer(0x1f); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3 }) */ + acpigen_write_return_singleton_buffer(0x3); acpigen_pop_len(); /* Pop : If */ /* Else */ acpigen_write_else(); - /* If (LEqual (Local2, 0x1)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); - /* Return (Buffer (One) { 0x3f }) */ - acpigen_write_return_singleton_buffer(0x3f); - acpigen_pop_len(); /* Pop : If */ - /* Else */ - acpigen_write_else(); /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); /* Pop : Else */ - acpigen_pop_len(); /* Pop : Else */ } static void i2c_hid_func1_cb(void *arg) -- To view, visit https://review.coreboot.org/c/coreboot/+/46429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56 Gerrit-Change-Number: 46429 Gerrit-PatchSet: 1 Gerrit-Owner: Josie Nordrum <josienordrum(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: FSP does not set subsystem
by Benjamin Doron (Code Review) 16 Oct '20

16 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45006 ) Change subject: soc/intel/skylake: FSP does not set subsystem ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Gerrit-Change-Number: 45006 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 18:21:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: disable eMMC per FW_CONFIG for berknip
by Kevin Chiu (Code Review) 16 Oct '20

16 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46292 ) Change subject: mb/google/zork: disable eMMC per FW_CONFIG for berknip ...................................................................... mb/google/zork: disable eMMC per FW_CONFIG for berknip Berknip has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/Makefile.inc A src/mainboard/google/zork/variants/berknip/variant.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46292/1 diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc index 57e7136..51d19fe 100644 --- a/src/mainboard/google/zork/variants/berknip/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/berknip/variant.c b/src/mainboard/google/zork/variants/berknip/variant.c new file mode 100644 index 0000000..092ff26 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Gerrit-Change-Number: 46292 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add support to override gpio config in bootblock
by Furquan Shaikh (Code Review) 16 Oct '20

16 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44586 ) Change subject: mb/google/dedede: Add support to override gpio config in bootblock ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG@7 PS5, Line 7: Add support to override gpio config in bootblock > I agree with Furquan's analysis. I have been burnt once for the same situation Furquan mentioned. […] I think the latter suggestion would be a safer one since it is easy to forget that the GPIO wasn't added to base table i.e. simply provide a stronger implementation of the GPIO table using variant_early_gpio_table() for the variant that requires a different early GPIO table than baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/44586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66949ef4d4e9772a86089b645883a94680108ee Gerrit-Change-Number: 44586 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 17:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add support to override gpio config in bootblock
by Karthik Ramasubramanian (Code Review) 16 Oct '20

16 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44586 ) Change subject: mb/google/dedede: Add support to override gpio config in bootblock ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG@7 PS5, Line 7: Add support to override gpio config in bootblock > Should we consider making a modification to the override mechanism to add entries from the override […] I agree with Furquan's analysis. I have been burnt once for the same situation Furquan mentioned. I forgot to configure the GPIO in the baseboard early gpio table and the override was not applying. For the use-case here, we don't need an early override table. GPIOs used for LTE power sequencing is dedicated for WWAN purposes. Those GPIOs can be configured in the baseboard early gpio table and overridden only in the ramstage. But if the use-case for these GPIOs change in the future and if we have to configure them in bootblock, then we will be in the same situation as we are today. >> Should we consider making a modification to the override mechanism to add entries from the override table that aren't in the base table? We can do it, but does that bode well with the definition of "override". My understanding is to override something we have to have a base definition. Without the base definition, do we want to allow overriding entries. An alternate option is to override the entire early gpio table. variant_early_gpio_table() is overrideable. So define a complete override table in the variant and return that. const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66949ef4d4e9772a86089b645883a94680108ee Gerrit-Change-Number: 44586 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 17:49:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Benjamin Doron (Code Review) 16 Oct '20

16 Oct '20

Hello build bot (Jenkins), Nico Huber, Frans Hendriks, Angel Pons, Patrick Rudolph, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45001 to look at the new patch set (#6). Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... soc/intel/skylake: Rename PcieRpAspm devicetree config This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/facebook/monolith/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45001/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Matt DeVillier (Code Review) 16 Oct '20

16 Oct '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > IMO a cleaner approach would be to move the code to a function in the MSR common block, switch any boards disabling ISST to use the function directly vs setting DT register, and then dropping from the SoC code > > Cleaner? How could useless code be cleaner than no code? perhaps i was unclear, I meant in conjunction with the parent commit. And the code wouldn't be useless, it would be used by google/dedede -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 14:50:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add support to override gpio config in bootblock
by Tim Wawrzynczak (Code Review) 16 Oct '20

16 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44586 ) Change subject: mb/google/dedede: Add support to override gpio config in bootblock ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG@7 PS5, Line 7: Add support to override gpio config in bootblock > variant_override_gpio_table is a similar implementation and adopted by multiple platforms already. […] Should we consider making a modification to the override mechanism to add entries from the override table that aren't in the base table? -- To view, visit https://review.coreboot.org/c/coreboot/+/44586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66949ef4d4e9772a86089b645883a94680108ee Gerrit-Change-Number: 44586 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 14:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: only lock AES-NI when supported
by Tim Wawrzynczak (Code Review) 16 Oct '20

16 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46276 ) Change subject: cpu/intel/common: only lock AES-NI when supported ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46276/6/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46276/6/src/cpu/intel/common/commo… PS6, Line 278: cpuid_ecx(1) `cpu_get_feature_flags_ecx` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/46276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Gerrit-Change-Number: 46276 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 16 Oct 2020 14:38:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Furquan Shaikh (Code Review) 16 Oct '20

16 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 9 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 14:08:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020