Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 )
Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence
......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
PS7, Line 39: PAD_CFG_GPO(GPP_H17, 1, PLTRST),
Do we make sure the nature boot time from bootblock to ramstage here is larger than 20ms?
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/boten/variant.c:
https://review.coreboot.org/c/coreboot/+/44588/7/src/mainboard/google/deded…
PS7, Line 35: saving one transaction to the EC for getting SKU ID.
Looks like the checking of SKU ID for LTE functionality is not added yet.
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44587 )
Change subject: mb/google/dedede: Add support for variant specific SMI sleep flow
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Patch Set 5: Code-Review+2
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Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44586 )
Change subject: mb/google/dedede: Add support to override gpio config in bootblock
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Before learning more from Furquan, +1 first since this mechanism was in Octopus platform reviewed by Furquan as well.
https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/44586/5//COMMIT_MSG@7
PS5, Line 7: Add support to override gpio config in bootblock
> This generally doesn't work well and results into lot of manual errors. […]
variant_override_gpio_table is a similar implementation and adopted by multiple platforms already. As a result, I thought this is just another version in bootblock stage?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 )
Change subject: soc/intel/icl: enable common CPU code
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms…
File src/soc/intel/icelake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms…
PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
> There is no `if`, when we use variant 1. set_vmx_and_lock() must be called explicitly in soc code. […]
Assuming 1) and VMX would be disabled. Wouldn't we need to call something
to lock in that case?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46467 )
Change subject: soc/intel/common/acpi: correct indentation
......................................................................
Patch Set 3: Code-Review+2
I just compare the binaries directly, hashing is just another step that could go wrong 😄
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46467
to look at the new patch set (#3).
Change subject: soc/intel/common/acpi: correct indentation
......................................................................
soc/intel/common/acpi: correct indentation
Test: built google/volteer with `abuild --timeless` - SHA1 hashes match
Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/acpi/lpit.asl
1 file changed, 69 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46467/3
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