coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Frans Hendriks (Code Review) 16 Oct '20

16 Oct '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 4: (2 comments) Cosmetic issue: Remove the 'extra' empty lines https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/51nb/x210/de… File src/mainboard/51nb/x210/devicetree.cb: https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/51nb/x210/de… PS4, Line 31: Remove the 'extra'empty line also https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/facebook/mon… File src/mainboard/facebook/monolith/devicetree.cb: https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/facebook/mon… PS4, Line 32: Same here remove 'empty' line -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Oct 2020 05:46:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: Assign memory strap GPIOs for boldar
by Aamir Bohra (Code Review) 16 Oct '20

16 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46132 ) Change subject: mb/google/volteer: Assign memory strap GPIOs for boldar ...................................................................... mb/google/volteer: Assign memory strap GPIOs for boldar Change-Id: Ib8dd47abed21c42652a1804470fcbf5bb19ebe29 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46132/1 diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h index b5fa8c5..72098b0 100644 --- a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h @@ -6,10 +6,9 @@ #include <baseboard/gpio.h> /* Memory configuration board straps */ -/* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_0 GPP_A7 +#define GPIO_MEM_CONFIG_1 GPP_A20 +#define GPIO_MEM_CONFIG_2 GPP_A19 #define GPIO_MEM_CONFIG_3 GPP_D15 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8dd47abed21c42652a1804470fcbf5bb19ebe29 Gerrit-Change-Number: 46132 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/intel/adlrvp: Enable Hybrid storage mode
by Subrata Banik (Code Review) 16 Oct '20

16 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46420 ) Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ...................................................................... mb/intel/adlrvp: Enable Hybrid storage mode TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46420/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index fadf602..c5103ce 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -72,6 +72,9 @@ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff" + # Hybrid storage mode + register "HybridStorageMode" = "1" + register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/46420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Gerrit-Change-Number: 46420 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mb/intel/adlrvp: Enable PCIE RP11 for optane
by Subrata Banik (Code Review) 16 Oct '20

16 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46419 ) Change subject: mb/intel/adlrvp: Enable PCIE RP11 for optane ...................................................................... mb/intel/adlrvp: Enable PCIE RP11 for optane Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46419/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index afa4c19..fadf602 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -59,6 +59,9 @@ register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" + # Enable PCH PCIE RP 11 for optane + register "PcieRpEnable[10]" = "1" + # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" @@ -241,7 +244,7 @@ device pci 1c.7 off end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 - device pci 1d.2 off end # RP11 + device pci 1d.2 on end # RP11 device pci 1d.3 off end # RP12 device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Gerrit-Change-Number: 46419 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/intel/adlrvp: Fix SSD detection issue on ADL RVP
by Subrata Banik (Code Review) 16 Oct '20

16 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46418 ) Change subject: mb/intel/adlrvp: Fix SSD detection issue on ADL RVP ...................................................................... mb/intel/adlrvp: Fix SSD detection issue on ADL RVP Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46418/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 7025b76..afa4c19 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -43,7 +43,7 @@ # Enable PCH PCIE RP 5 using CLK 2 register "PcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcUsage[2]" = "0x4" register "PcieRpClkReqDetect[4]" = "1" @@ -55,7 +55,7 @@ # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/46418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Gerrit-Change-Number: 46418 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/intel/adlrvp: Program GPIO for M.2 PCH SSD
by Subrata Banik (Code Review) 16 Oct '20

16 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46417 ) Change subject: mb/intel/adlrvp: Program GPIO for M.2 PCH SSD ...................................................................... mb/intel/adlrvp: Program GPIO for M.2 PCH SSD This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46417/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index 5a21992..e142e88 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -70,7 +70,11 @@ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* Sata direct Power */ PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* THC0 SPI1 CLK */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), /* THC0 SPI1 IO 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Gerrit-Change-Number: 46417 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: include/cpu/x86: introduce new helper for (un)setting MSRs
by Nico Huber (Code Review) 16 Oct '20

16 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46354 ) Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Gerrit-Change-Number: 46354 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 23:29:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Nico Huber (Code Review) 16 Oct '20

16 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… File src/soc/intel/icelake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX); > always call the lock when fsp already locks it? I don't think we want this duplication Better than yet another `if`? -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 15 Oct 2020 23:02:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cnl: lock AES-NI feature if selected
by Nico Huber (Code Review) 16 Oct '20

16 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46273 ) Change subject: soc/intel/cnl: lock AES-NI feature if selected ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/46273/6/src/soc/intel/cannonlake/K… File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/c/coreboot/+/46273/6/src/soc/intel/cannonlake/K… PS6, Line 81: select CPU_INTEL_COMMON_HYPERTHREADING > Not sure what you mean with "assume it's `y`" What if we would remove the whole Kconfig option and act as if it was set to `y`? -- To view, visit https://review.coreboot.org/c/coreboot/+/46273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Gerrit-Change-Number: 46273 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 22:59:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Karthik Ramasubramanian (Code Review) 16 Oct '20

16 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/45912/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45912/8//COMMIT_MSG@9 PS8, Line 9: > an Done https://review.coreboot.org/c/coreboot/+/45912/8/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/45912/8/src/mainboard/google/deded… PS8, Line 125: ACPI_GPIO_OUTPUT_ACTIVE_HIGH > I think this should be just ACPI_GPIO_OUTPUT. Polarity doesn't really mean anything here. Agree. Also the polarity settings of ACPI_GPIO_OUTPUT and ACPI_GPIO_OUTPUT_ACTIVE_HIGH are same. -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 9 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 22:54:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020