Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
PS6, Line 286: msr_set
> msr_set_bit ?
Done
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
PS6, Line 286: AESNI_LOCK
> then this would still need to be zero (not 1<<0), msr_set_bits takes a bit index and does the shifti […]
you missed CB:46354 ;)
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.…
PS4, Line 9: (1 << 0)
> How about `BIT(0)` ? (would require #include <types. […]
we shouldn't mix it; this is the way it's done most of the times in headers; see x86/msr.h for example or intelblocks/msr.h
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Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: comment
Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46354
to look at the new patch set (#6).
Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs
......................................................................
include/cpu/x86: introduce new helper for (un)setting MSRs
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/haswell/finalize.c
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_206ax/finalize.c
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/msr.h
6 files changed, 48 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46354/6
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
PS6, Line 286: AESNI_LOCK
then this would still need to be zero (not 1<<0), msr_set_bits takes a bit index and does the shifting itself
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/commo…
PS6, Line 286: msr_set
msr_set_bit ?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 )
Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 9: #define AESNI_LOCK_BIT 0
> sounds like a plan
Done
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Gerrit-MessageType: comment
Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46277
to look at the new patch set (#6).
Change subject: cpu/intel/common: add a Kconfig to control AES-NI locking
......................................................................
cpu/intel/common: add a Kconfig to control AES-NI locking
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging,
testing, ...
Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/Kconfig
M src/cpu/intel/common/common_init.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46277/6
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46276
to look at the new patch set (#6).
Change subject: cpu/intel/common: only lock AES-NI when supported
......................................................................
cpu/intel/common: only lock AES-NI when supported
Add a check to only lock AES-NI when AES is supported.
Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common_init.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46276/6
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46275
to look at the new patch set (#6).
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
cpu/intel/common: rework AES-NI locking
Simplify the AES-NI code by using msr_set and correct the comment.
Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/cpu/intel/msr.h
3 files changed, 10 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46275/6
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 )
Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45912/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45912/8//COMMIT_MSG@9
PS8, Line 9:
an
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Gerrit-Comment-Date: Thu, 15 Oct 2020 22:13:18 +0000
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 )
Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45912/8/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/waddledee/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45912/8/src/mainboard/google/deded…
PS8, Line 125: ACPI_GPIO_OUTPUT_ACTIVE_HIGH
I think this should be just ACPI_GPIO_OUTPUT. Polarity doesn't really mean anything here.
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