coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc… PS17, Line 45: TCO > no response -> I guess this isn't that important? feel free to reopen Sorry for overlooking this. In my opinion, it does not hurt to spell it out once, and it’s easier for new users, which look through the options. -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 17 Oct 2020 21:57:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 20: (2 comments) https://review.coreboot.org/c/coreboot/+/45952/19//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45952/19//COMMIT_MSG@25 PS19, Line 25: unknown if that is desireable on that platform. > It's reserved/ro 0, and BIOS spec says there is none. Done https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc… PS17, Line 45: TCO > what for? this is not even done for block/smbus/Kconfig or block/smm/Kconfig no response -> I guess this isn't that important? feel free to reopen -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 17 Oct 2020 21:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Michael Niewöhner (Code Review) 17 Oct '20

17 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG@9 PS8, Line 9: This converts the constant for the XTAL frequency to a Kconfig option. > Oh btw. this was done first to make the buildbot pass for socs without that value defined. […] no more info since 11 days -> I assume resolved. feel free to reopen -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 20:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Use MCHBAR register names on finalize
by Angel Pons (Code Review) 17 Oct '20

17 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46526 ) Change subject: soc/intel/broadwell: Use MCHBAR register names on finalize ...................................................................... soc/intel/broadwell: Use MCHBAR register names on finalize Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7274334ff3ce2d9887cc3d8a1ba54a9c52286cc4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/include/soc/systemagent.h 2 files changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46526/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index fe3dfb6..869b767 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -37,24 +37,24 @@ pci_or_config32(host_bridge, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(host_bridge, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32(0x5500) |= 1 << 0; - MCHBAR32(0x5f00) |= 1 << 31; - MCHBAR32(0x6020) |= 1 << 0; - MCHBAR32(0x63fc) |= 1 << 0; - MCHBAR32(0x6800) |= 1 << 31; - MCHBAR32(0x7000) |= 1 << 31; - MCHBAR32(0x77fc) |= 1 << 0; + MCHBAR32(MMIO_PAVP_MSG) |= 1 << 0; + MCHBAR32(SAPMCTL) |= 1 << 31; + MCHBAR32(UMAGFXCTL) |= 1 << 0; + MCHBAR32(VTDTRKLCK) |= 1 << 0; + MCHBAR32(REQLIM) |= 1 << 31; + MCHBAR32(DMIVCLIM) |= 1 << 31; + MCHBAR32(CRDTLCK) |= 1 << 0; /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; + MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); /* This is a lock bit, but does not appear in the SA locking sequence */ - MCHBAR32(0x5880) |= 1 << 5; + MCHBAR32(PCU_DDR_PTM_CTL) |= 1 << 5; } const struct reg_script pch_finalize_script[] = { diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index c2c5cc8..52d386b 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -85,6 +85,9 @@ #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR_PEI_VERSION 0x5034 + +#define MC_LOCK 0x50fc + #define BIOS_RESET_CPL 0x5da8 #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 @@ -92,11 +95,26 @@ #define MCH_PAIR 0x5418 #define GDXCBAR 0x5420 +#define MMIO_PAVP_MSG 0x5500 + +#define PCU_DDR_PTM_CTL 0x5880 + #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define SAPMCTL 0x5f00 + +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define CRDTLCK 0x77fc + /* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 #define MAILBOX_RUN_BUSY (1 << 31) -- To view, visit https://review.coreboot.org/c/coreboot/+/46526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7274334ff3ce2d9887cc3d8a1ba54a9c52286cc4 Gerrit-Change-Number: 46526 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/libpci: Store device class in pci_dev
by Felix Singer (Code Review) 17 Oct '20

17 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46347 ) Change subject: libpayload/libpci: Store device class in pci_dev ...................................................................... libpayload/libpci: Store device class in pci_dev Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M payloads/libpayload/include/pci/pci.h M payloads/libpayload/libpci/libpci.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46347/1 diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 37aeafa..ea11a05 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -74,6 +74,7 @@ u16 domain; u8 bus, dev, func; u16 vendor_id, device_id; + u16 device_class; struct pci_dev *parent; struct pci_dev *next; }; diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 50cd228..b8188a1 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -182,6 +182,7 @@ dev->func = func; dev->vendor_id = val & 0xffff; dev->device_id = (uint16_t)(val >> 16); + dev->device_class = pci_read_config16(PCI_DEV(bus, slot, func), 0xa); dev->next = 0; hdr = pci_read_config8(PCI_DEV(bus, slot, func), -- To view, visit https://review.coreboot.org/c/coreboot/+/46347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Gerrit-Change-Number: 46347 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/libpci: Clean up pci_alloc()
by Nico Huber (Code Review) 17 Oct '20

17 Oct '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46345 ) Change subject: libpayload/libpci: Clean up pci_alloc() ...................................................................... libpayload/libpci: Clean up pci_alloc() Clean up pci_alloc() and return pointer to allocated memory directly. Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M payloads/libpayload/libpci/libpci.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 27347e3..3e3513c 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -72,8 +72,7 @@ struct pci_access *pci_alloc(void) { - struct pci_access *pacc = malloc(sizeof(*pacc)); - return pacc; + return malloc(sizeof(struct pci_access)); } void pci_init(struct pci_access *pacc) -- To view, visit https://review.coreboot.org/c/coreboot/+/46345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Gerrit-Change-Number: 46345 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: superio: Add newline to log message about disabled mouse controller
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45805 ) Change subject: superio: Add newline to log message about disabled mouse controller ...................................................................... superio: Add newline to log message about disabled mouse controller A newline is missing at the end of the informational message. PNP: 002e.5 init nct5572d_init: Disable mouse controller.PNP: 002e.5 init finished in 0 msecs PNP: 002e.307 init Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Fixes: 6ff1078990 ("superio: Log if mouse controller is disabled") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83667hg-a/superio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45805/1 diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 351181c..c0a7118 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -36,7 +36,7 @@ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index bea2101..828fe9a 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -36,7 +36,7 @@ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); -- To view, visit https://review.coreboot.org/c/coreboot/+/45805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Gerrit-Change-Number: 45805 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: AMD mb: AMD CIMx boards: Fix typo in *is defined* in comments
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46066 ) Change subject: AMD mb: AMD CIMx boards: Fix typo in *is defined* in comments ...................................................................... AMD mb: AMD CIMx boards: Fix typo in *is defined* in comments The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/inagua/platform_cfg.h M src/mainboard/amd/persimmon/platform_cfg.h M src/mainboard/amd/south_station/platform_cfg.h M src/mainboard/amd/union_station/platform_cfg.h M src/mainboard/asrock/e350m1/platform_cfg.h M src/mainboard/elmex/pcm205400/platform_cfg.h M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h M src/mainboard/lippert/frontrunner-af/platform_cfg.h M src/mainboard/pcengines/apu1/platform_cfg.h 10 files changed, 110 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46066/1 diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 38447ac..85a60e2 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index d472ad0..32c22bc 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 38447ac..85a60e2 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 38447ac..85a60e2 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6d3ea82..6994575 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index b621f60b..7926249 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 2ea529f..af7da08 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -40,13 +40,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -143,13 +143,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index bacb7b1..9c8d0f6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 9f51c40..ba6f0bb 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define USB_CONFIG 0x3F @@ -148,13 +148,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ #if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define AZALIA_SDIN_PIN 0x02 diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index ef6f5ba..44172f6 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -39,13 +39,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -141,13 +141,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A -- To view, visit https://review.coreboot.org/c/coreboot/+/46066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Gerrit-Change-Number: 46066 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: vendorcode/amd: Fix typo in *is defined* in comments
by Paul Menzel (Code Review) 17 Oct '20

17 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46065 ) Change subject: vendorcode/amd: Fix typo in *is defined* in comments ...................................................................... vendorcode/amd: Fix typo in *is defined* in comments The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. $ git grep -l "is define at" src/vendorcode/amd/ | xargs sed -i 's/is define at/is defined at/' Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/cimx/sb800/SBTYPE.h M src/vendorcode/amd/cimx/sb900/SbType.h M src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h 8 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46065/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h index be373c7..bc755f0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h @@ -140,19 +140,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h index 9009f6b..b318665 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h @@ -145,19 +145,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index b897950..2fa7923 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -538,25 +538,25 @@ /** _USBST Controller structure * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -578,25 +578,25 @@ typedef struct _AZALIAPIN { unsigned char AzaliaSdin0:2; /**< AzaliaSdin0 * @par - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin1:2; /**< AzaliaSdin1 * @par - * SDIN0 is define at BIT2 & BIT3 + * SDIN0 is defined at BIT2 & BIT3 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin2:2; /**< AzaliaSdin2 * @par - * SDIN0 is define at BIT4 & BIT5 + * SDIN0 is defined at BIT4 & BIT5 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin3:2; /**< AzaliaSdin3 * @par - * SDIN0 is define at BIT6 & BIT7 + * SDIN0 is defined at BIT6 & BIT7 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ @@ -718,25 +718,25 @@ /** USBDeviceConfig - USB Controller Configuration * - * - Usb Ohci1 Contoller is define at BIT0 + * - Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * - Usb Ehci1 Contoller is define at BIT1 + * - Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * - Usb Ohci2 Contoller is define at BIT2 + * - Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * - Usb Ehci2 Contoller is define at BIT3 + * - Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * - Usb Ohci3 Contoller is define at BIT4 + * - Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * - Usb Ehci3 Contoller is define at BIT5 + * - Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * - Usb Ohci4 Contoller is define at BIT6 + * - Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -816,16 +816,16 @@ { /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration * - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * - 00: GPIO PIN * - 01: Reserved * - 10: As a Azalia SDIN pin * - * SDIN1 is define at BIT2 & BIT3 + * SDIN1 is defined at BIT2 & BIT3 * * Config same as SDIN0 - * SDIN2 is define at BIT4 & BIT5 + * SDIN2 is defined at BIT4 & BIT5 * * Config same as SDIN0 - * SDIN3 is define at BIT6 & BIT7 + * SDIN3 is defined at BIT6 & BIT7 * * Config same as SDIN0 */ unsigned char AzaliaSdinPin; diff --git a/src/vendorcode/amd/cimx/sb900/SbType.h b/src/vendorcode/amd/cimx/sb900/SbType.h index 87f49bd..eeedbba 100644 --- a/src/vendorcode/amd/cimx/sb900/SbType.h +++ b/src/vendorcode/amd/cimx/sb900/SbType.h @@ -613,25 +613,25 @@ /** _USBST Controller structure * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -684,25 +684,25 @@ unsigned char AzaliaSdinPin; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry unsigned char AzaliaSdin0; /**< AzaliaSdin0 * @par - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin1; /**< AzaliaSdin1 * @par - * SDIN0 is define at BIT2 & BIT3 + * SDIN0 is defined at BIT2 & BIT3 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin2; /**< AzaliaSdin2 * @par - * SDIN0 is define at BIT4 & BIT5 + * SDIN0 is defined at BIT4 & BIT5 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin3; /**< AzaliaSdin3 * @par - * SDIN0 is define at BIT6 & BIT7 + * SDIN0 is defined at BIT6 & BIT7 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ @@ -927,25 +927,25 @@ /** USBDeviceConfig - USB Controller Configuration * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -1021,16 +1021,16 @@ { /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration 00-51 * - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * - 00: GPIO PIN * - 01: Reserved * - 10: As a Azalia SDIN pin * - * SDIN1 is define at BIT2 & BIT3 + * SDIN1 is defined at BIT2 & BIT3 * * Config same as SDIN0 - * SDIN2 is define at BIT4 & BIT5 + * SDIN2 is defined at BIT4 & BIT5 * * Config same as SDIN0 - * SDIN3 is define at BIT6 & BIT7 + * SDIN3 is defined at BIT6 & BIT7 * * Config same as SDIN0 */ unsigned char AzaliaSdinPin; diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h index 39a11ba..b10eca7 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h @@ -148,19 +148,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h index 35a76d2..8c557bc 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -177,19 +177,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h index 21f73a3..6dcfb7e 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h @@ -182,19 +182,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h index 72e6aeb..f96dfdb 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h @@ -152,19 +152,19 @@ UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; -- To view, visit https://review.coreboot.org/c/coreboot/+/46065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56 Gerrit-Change-Number: 46065 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020