coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: util/sconfig: allow to override chip-wrapped devices
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46531 to look at the new patch set (#6). Change subject: util/sconfig: allow to override chip-wrapped devices ...................................................................... util/sconfig: allow to override chip-wrapped devices Currently, when a overridetree disables a device wrapped by a chip driver in the base tree, without having the same wrapping chip, sconfig mistakenly creates two instances of the same device. This leads to a conflict. The following example shows that: base tree: chip soc/intel/whateverlake device domain 0 on chip drivers/wifi/generic device pci 14.3 on end end end end overridetree: ... device pci 14.3 off end ... The static.[ch] then contains two declarations of the same device: extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_14_3; ... extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_14_3; The same problem appears with the newly introduced chipset devicetrees, that only include the device without chip driver. An overridetree wrapping such device by a chip driver - which the same example above with swapped base and overridetree represents - will lead to the same problem. To cover such use cases, move the match check for chip drivers into the device update procedure and override the base chip accordingly if the chip driver does not match. If the chip driver matches, there is no change to the original behaviour. Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M util/sconfig/main.c 1 file changed, 38 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46531/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Gerrit-Change-Number: 46531 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/dnv_ns: enable common CPU code
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46474 ) Change subject: soc/intel/dnv_ns: enable common CPU code ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/46474/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46474/3//COMMIT_MSG@12 PS3, Line 12: copy pasta from ICl TBD : Note: This also retrieves the VMX Kconfig and enables it by default, : like done for SKL and CNL already. : : TODO: AFAICT VMX is not supported on denverton ns. not sure about fc. I : was unable to hide the Kconfig without adding some CPU_SUPPORTS_... : : TODO -- To view, visit https://review.coreboot.org/c/coreboot/+/46474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab556055fb229a7e3387ddbd4ff1cb461e36f7b2 Gerrit-Change-Number: 46474 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Oct 2020 00:15:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG@13 PS5, Line 13: like done for SKL,ICL,... already. > > This isn't quite clear, IMHO. "like done for [...]ICL"? but this is ICL. […] well.... ENABLE_VMX is already hooked up since 2ee8fe0 https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… File src/soc/intel/icelake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX); > Yes exactly, unfortunately the first was wrong, because for some reason I saw a return where none is […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 18 Oct 2020 00:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45826 to look at the new patch set (#11). Change subject: soc/intel/icl: enable common CPU code ...................................................................... soc/intel/icl: enable common CPU code Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/icelake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45826/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/51nb/x210/de… File src/mainboard/51nb/x210/devicetree.cb: https://review.coreboot.org/c/coreboot/+/46462/4/src/mainboard/51nb/x210/de… PS4, Line 31: > Remove the 'extra'empty line also Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 23:29:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Frans Hendriks, Jeremy Soller, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46462 to look at the new patch set (#5). Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 49 files changed, 2 insertions(+), 118 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46462/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel/model_{2065x,206ax}: fix AES-NI locking
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46535 ) Change subject: cpu/intel/model_{2065x,206ax}: fix AES-NI locking ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Gerrit-Change-Number: 46535 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 23:20:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/21//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45952/21//COMMIT_MSG@21 PS21, Line 21: Note: On Apollolake USE_PM_ACPI_TIMER gets selected statically to avoid : confusing the user in menuconfig, where the option is shown due to use : of the common code for PM Timer emulation. On APL there is not hardware : PM ACPI Timer, so emulation needs to be always enabled. : needs rework, when we decide to hide USE_PM_ACPI_TIMER somehow -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 23:17:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/apollolake/… File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/apollolake/… PS21, Line 108: select USE_PM_ACPI_TIMER > oh, we can drop that now... hmm... hiding USE_PM_ACPI_TIMER isn't possible easily, because the soc Kconfig can't override it :S We could add another Kconfig CPU_HAS_PM_ACPI_TIMER but.... -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 23:14:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 21: (2 comments) https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/apollolake/… File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/apollolake/… PS21, Line 108: select USE_PM_ACPI_TIMER oh, we can drop that now... https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/common/bloc… File src/soc/intel/common/block/pmc/Kconfig: https://review.coreboot.org/c/coreboot/+/45952/21/src/soc/intel/common/bloc… PS21, Line 46: Disabling it enables the ACPI timer emulation in microcode this is not true anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Oct 2020 23:08:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020