coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: util/abuild/abuild: Do not check out submodules
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45607 ) Change subject: util/abuild/abuild: Do not check out submodules ...................................................................... util/abuild/abuild: Do not check out submodules This force-downloads the qc_blobs repository, whose license is then automatically accepted. This may also cause race conditions with git. Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/abuild/abuild 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/45607/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 7561495..2ba2f72 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -794,8 +794,6 @@ echo | xargs -P ${cpus:-0} -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 fi -git submodule update --checkout --init - if [ "$USE_XARGS" = "0" ]; then test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus" export MAKEFLAGS="$MAKEFLAGS UPDATED_SUBMODULES=1" # no need to re-download -- To view, visit https://review.coreboot.org/c/coreboot/+/45607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec Gerrit-Change-Number: 45607 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: Documentation: Fix spelling of *assumptions*
by Paul Menzel (Code Review) 19 Oct '20

19 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33742 Change subject: Documentation: Fix spelling of *assumptions* ...................................................................... Documentation: Fix spelling of *assumptions* Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/arch/x86/index.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33742/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 0d8acf1..b4ad5c8 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -17,7 +17,7 @@ The following features enhance x86_64 support: * The CPU supports 1GiB hugepages -## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation +## Assumptions for ARCH_ROMSTAGE_X86_64 reference implementation * 0-4GiB are identity mapped as WB * Memory above 4GiB isn't accessible * pagetables reside in CAR area `_pagetables` @@ -38,7 +38,7 @@ * 0-4GiB are identity mapped as WB * page tables reside in heap -## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation +## Assumptions for ARCH_RAMSTAGE_X86_64 reference implementation * pagetable are stored in fixed size heap area, initialized by assembly code * Memory above 4GiB is not accessible -- To view, visit https://review.coreboot.org/c/coreboot/+/33742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Gerrit-Change-Number: 33742 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: sb/intel/ibexpeak: Use ARRAY_SIZE macro
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46529 ) Change subject: sb/intel/ibexpeak: Use ARRAY_SIZE macro ...................................................................... sb/intel/ibexpeak: Use ARRAY_SIZE macro Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46529/1 diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 55dcb02..d4f1925 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -293,7 +293,7 @@ /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 }; - for (i = 0; i < sizeof(rcba2010) / sizeof(rcba2010[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2010); i++) { RCBA32 (0x2010 + 4 * i) = rcba2010[i]; RCBA32 (0x2010 + 4 * i); @@ -331,7 +331,7 @@ /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 }; - for (i = 0; i < sizeof(rcba2210) / sizeof(rcba2210[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { RCBA32 (0x2210 + 4 * i) = rcba2210[i]; RCBA32 (0x2210 + 4 * i); @@ -344,7 +344,7 @@ /* 2320: */ 0xcccc0cfc, 0x0fbb0fff }; - for (i = 0; i < sizeof(rcba2300) / sizeof(rcba2300[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { RCBA32 (0x2300 + 4 * i) = rcba2300[i]; RCBA32 (0x2300 + 4 * i); -- To view, visit https://review.coreboot.org/c/coreboot/+/46529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Gerrit-Change-Number: 46529 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: superio/nuvoton: Factor out equivalent Kconfig option
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46522 ) Change subject: superio/nuvoton: Factor out equivalent Kconfig option ...................................................................... superio/nuvoton: Factor out equivalent Kconfig option There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asus/p8h61-m_lx/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig M src/mainboard/supermicro/x9scl/Kconfig M src/superio/nuvoton/common/Kconfig M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/nct5539d/Kconfig M src/superio/nuvoton/nct6776/Kconfig M src/superio/nuvoton/nct6791d/Kconfig 11 files changed, 14 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46522/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index a80b595..d923c30 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -11,8 +11,8 @@ select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 6406417..af723a3 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -17,8 +17,8 @@ select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE hex diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 069800a..a108c3b 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -17,8 +17,8 @@ select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select USE_NATIVE_RAMINIT config MAINBOARD_DIR diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f81dbee..873f257 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -11,8 +11,8 @@ select HAVE_OPTION_TABLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 598fbbe..5e09349 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -13,8 +13,8 @@ select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE hex diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index 9968d34..6261726 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -9,8 +9,8 @@ select RAMINIT_ENABLE_ECC select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select SUPERIO_NUVOTON_WPCM450 select MAINBOARD_USES_IFD_GBE_REGION select IPMI_KCS diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig index 413b6a6..78523c1 100644 --- a/src/superio/nuvoton/common/Kconfig +++ b/src/superio/nuvoton/common/Kconfig @@ -5,6 +5,13 @@ config SUPERIO_NUVOTON_COMMON_PRE_RAM bool +config SUPERIO_NUVOTON_COMMON_COM_A + bool + depends on SUPERIO_NUVOTON_COMMON_PRE_RAM + help + When enabled, the 'nuvoton_enable_serial()' function will unset + global CR 0x2a bit 7 to route COM A to the GPIO8 pin group. + # Generic Nuvoton HWM driver config SUPERIO_NUVOTON_COMMON_HWM bool diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 3986789..f86e7a2 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -52,9 +52,7 @@ nuvoton_pnp_enter_conf_state(dev); - if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || - CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A) || - CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) + if (CONFIG(SUPERIO_NUVOTON_COMMON_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0); diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig index 440775f..dc48246 100644 --- a/src/superio/nuvoton/nct5539d/Kconfig +++ b/src/superio/nuvoton/nct5539d/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT5539D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT5539D_COM_A - bool - depends on SUPERIO_NUVOTON_NCT5539D - default n diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig index caa89b3..9f5e084 100644 --- a/src/superio/nuvoton/nct6776/Kconfig +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT6776 bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT6776_COM_A - bool - depends on SUPERIO_NUVOTON_NCT6776 - default n diff --git a/src/superio/nuvoton/nct6791d/Kconfig b/src/superio/nuvoton/nct6791d/Kconfig index b06ee31..a536491 100644 --- a/src/superio/nuvoton/nct6791d/Kconfig +++ b/src/superio/nuvoton/nct6791d/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT6791D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT6791D_COM_A - bool - depends on SUPERIO_NUVOTON_NCT6791D - default n -- To view, visit https://review.coreboot.org/c/coreboot/+/46522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Gerrit-Change-Number: 46522 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: util/supermicro: Always include commonlib/bsd/compiler.h
by Nico Huber (Code Review) 19 Oct '20

19 Oct '20

Hello Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41784 to review the following change. Change subject: util/supermicro: Always include commonlib/bsd/compiler.h ...................................................................... util/supermicro: Always include commonlib/bsd/compiler.h We rely on `compiler.h` for definitions like `__packed`. Without it, `smcbiosinfo.c` simply declared a global struct with that name, but nothing was packed. Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/supermicro/Makefile.inc 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41784/1 diff --git a/util/supermicro/Makefile.inc b/util/supermicro/Makefile.inc index 1aa5bcb..316cb48 100644 --- a/util/supermicro/Makefile.inc +++ b/util/supermicro/Makefile.inc @@ -1,9 +1,11 @@ +TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + SMCBIOSINFOTOOL:= $(objutil)/supermicro/smcbiosinfo $(SMCBIOSINFOTOOL): $(dir)/smcbiosinfo/smcbiosinfo.c printf " HOSTCC Creating SMCBIOSINFO tool\n" mkdir -p $(objutil)/supermicro - $(HOSTCC) $< -o $@ + $(HOSTCC) $(TOOLCPPFLAGS) $< -o $@ ifeq ($(CONFIG_VENDOR_SUPERMICRO),y) ifneq ($(call strip_quotes, $(CONFIG_SUPERMICRO_BOARDID)),) -- To view, visit https://review.coreboot.org/c/coreboot/+/41784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc Gerrit-Change-Number: 41784 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: volteer+vendorcode: Cr50 version code only via SPI
by Jes Klinke (Code Review) 19 Oct '20

19 Oct '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46436 to review the following change. Change subject: volteer+vendorcode: Cr50 version code only via SPI ...................................................................... volteer+vendorcode: Cr50 version code only via SPI No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempts to do so unconditionally. This CL makes it such that the code also compiles in case future designs will use I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM, which will be connected via I2C in the upcoming designs. TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk(a)chromium.org --- M src/mainboard/google/volteer/mainboard.c M src/vendorcode/google/chromeos/cse_board_reset.c 2 files changed, 21 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/46436/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1fcd5eb..1abb636 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -51,7 +51,8 @@ return; } - if (cr50_is_long_interrupt_pulse_enabled()) { + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) + && cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c index 65e09ae..0b213a6 100644 --- a/src/vendorcode/google/chromeos/cse_board_reset.c +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -16,24 +16,27 @@ int ret; struct cr50_firmware_version version; - /* Initialize TPM and get the cr50 firmware version. */ - ret = tlcl_lib_init(); - if (ret != VB2_SUCCESS) { - printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); - return; + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* Initialize TPM and get the cr50 firmware version. */ + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + cr50_get_firmware_version(&version); + + /* + * Cr50 firmware versions 0.[3|4].20 or newer support strap + * config 0xe where PLTRST from AP is connected to cr50's + * PLTRST# signal. So return immediately and trigger a global + * reset. + */ + if (version.epoch != 0 || version.major > 4 || + (version.major >= 3 && version.minor >= 20)) + return; } - cr50_get_firmware_version(&version); - - /* - * Cr50 firmware versions 0.[3|4].20 or newer support strap config 0xe where PLTRST from - * AP is connected to cr50's PLTRST# signal. So return immediately and trigger a - * global reset. - */ - if (version.epoch != 0 || version.major > 4 || - (version.major >= 3 && version.minor >= 20)) - return; - printk(BIOS_INFO, "Initiating request to EC to trigger cold reset\n"); /* * Clean the data cache and set the full reset bit, so that when EC toggles -- To view, visit https://review.coreboot.org/c/coreboot/+/46436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Gerrit-Change-Number: 46436 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.h
by Shelley Chen (Code Review) 19 Oct '20

19 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46508 ) Change subject: security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.h ...................................................................... security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.h As ongoing work for generalizing mrc_cache to be used by all platforms, we are pulling it out from fsp 2.0 and renaming it as mrc_cache_hash_tpm.h in security/vboot. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/security/vboot/mrc_cache_hash_tpm.c R src/security/vboot/mrc_cache_hash_tpm.h 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46508/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1ef9324..14aec98 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -20,8 +20,8 @@ #include <timestamp.h> #include <security/vboot/vboot_common.h> #include <security/tpm/tspi.h> +#include <security/vboot/mrc_cache_hash_tpm.h> #include <vb2_api.h> -#include <fsp/memory_init.h> #include <types.h> static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index bc500a2..24e7aaf 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -5,7 +5,7 @@ #include <security/vboot/vboot_common.h> #include <vb2_api.h> #include <security/tpm/tss.h> -#include <fsp/memory_init.h> +#include <security/vboot/mrc_cache_hash_tpm.h> #include <console/console.h> #include <string.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/security/vboot/mrc_cache_hash_tpm.h similarity index 77% rename from src/drivers/intel/fsp2_0/include/fsp/memory_init.h rename to src/security/vboot/mrc_cache_hash_tpm.h index e100efb..a1ecd8b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h +++ b/src/security/vboot/mrc_cache_hash_tpm.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _FSP2_0_MEMORY_INIT_H_ -#define _FSP2_0_MEMORY_INIT_H_ +#ifndef _MRC_CACHE_HASH_TPM_H_ +#define _MRC_CACHE_HASH_TPM_H_ #include <types.h> @@ -16,4 +16,4 @@ */ int mrc_cache_verify_hash(const uint8_t *data, size_t size); -#endif /* _FSP2_0_MEMORY_INIT_H_ */ +#endif /* _MRC_CACHE_HASH_TPM_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Gerrit-Change-Number: 46508 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/skylake: Do not let FSP set the subsystem IDs
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45006 ) Change subject: soc/intel/skylake: Do not let FSP set the subsystem IDs ...................................................................... soc/intel/skylake: Do not let FSP set the subsystem IDs The subsystem ID registers are read/write-once. Writes by coreboot will not take effect if FSP sets them. Note that FSP sets one device ID for the SA devices and another for PCH devices. coreboot will copy individual vendor and device IDs if subsystem is not provided. Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip.c 1 file changed, 5 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 549f403..89eaef5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -320,16 +320,11 @@ */ params->SpiFlashCfgLockDown = 0; } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } + /* FSP should let coreboot set subsystem IDs, which are read/write-once */ + params->DefaultSvid = 0; + params->PchSubSystemVendorId = 0; + params->DefaultSid = 0; + params->PchSubSystemId = 0; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; -- To view, visit https://review.coreboot.org/c/coreboot/+/45006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Gerrit-Change-Number: 45006 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Fix memory corruptions
by John Zhao (Code Review) 19 Oct '20

19 Oct '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46504 ) Change subject: Fix memory corruptions ...................................................................... Fix memory corruptions Coverity detects source memory is overrun. Fix this issue by using the correct source memory size to avoid memory corruption. Found-by: Coverity CID 1429762 1429774 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46504/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d66e890a..fe7641f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -355,14 +355,14 @@ memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + sizeof(config->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented, sizeof(config->PcieRpSlotImplemented)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + sizeof(config->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/46504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc Gerrit-Change-Number: 46504 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/common/acpi: correct indentation
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46467 ) Change subject: soc/intel/common/acpi: correct indentation ...................................................................... soc/intel/common/acpi: correct indentation Test: built google/volteer with `abuild --timeless` - SHA1 hashes match Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/acpi/lpit.asl 1 file changed, 69 insertions(+), 69 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl index 348ae56..6159685 100644 --- a/src/soc/intel/common/acpi/lpit.asl +++ b/src/soc/intel/common/acpi/lpit.asl @@ -24,80 +24,80 @@ Method(_DSM, 4) { If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) - } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(1) - } - - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(1) - } - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + * Enum functions */ - If (CondRefOf (\_SB.PCI0.EGPM)) - { - \_SB.PCI0.EGPM () + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } } } - /* - * Function 6 - Low Power S0 Exit Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(0) - } - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (\_SB.PCI0.RGPM)) - { - \_SB.PCI0.RGPM () - } - } - } - - Return(Buffer(One) {0x00}) + Return(Buffer(One) {0x00}) } // Method(_DSM) } // Device (LPID) } // End Scope(\_SB) -- To view, visit https://review.coreboot.org/c/coreboot/+/46467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Gerrit-Change-Number: 46467 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020