coreboot-gerrit October 2020

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Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Tim Wawrzynczak (Code Review) 19 Oct '20

19 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46463 ) Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... Patch Set 6: Code-Review+1 it does look fine, BTW -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Oct 2020 18:38:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Tim Wawrzynczak (Code Review) 19 Oct '20

19 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Oct 2020 18:37:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Tim Wawrzynczak (Code Review) 19 Oct '20

19 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46463 ) Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46463/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46463/6//COMMIT_MSG@14 PS6, Line 14: Test: Did you test this? -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Oct 2020 17:59:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: [REFERENCE] Make FMD changes to accomodate CSE RW blob
by Sridhar Siricilla (Code Review) 19 Oct '20

19 Oct '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46313 ) Change subject: mb/google/hatch: [REFERENCE] Make FMD changes to accomodate CSE RW blob ...................................................................... mb/google/hatch: [REFERENCE] Make FMD changes to accomodate CSE RW blob Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I435b918d46c2afc5866820067ad0ca834db1fee1 --- M src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46313/1 diff --git a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd b/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd index 8368b0a..69c69dd 100644 --- a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd @@ -10,13 +10,15 @@ RW_LEGACY(CBFS)@0x0 0x1000000 RW_SECTION_A@0x1000000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x28afc0 + RW_FWID_A@0x29afc0 0x40 + FW_MAIN_A_EXTN(CBFS)@0x29b000 0x145000 } RW_SECTION_B@0x13e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x28afc0 + RW_FWID_B@0x29afc0 0x40 + FW_MAIN_B_EXTN(CBFS)@0x29b000 0x145000 } RW_MISC@0x17c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/46313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435b918d46c2afc5866820067ad0ca834db1fee1 Gerrit-Change-Number: 46313 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/storage: Enable STORAGE_64BIT_LBA
by Felix Singer (Code Review) 19 Oct '20

19 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46534 ) Change subject: libpayload/storage: Enable STORAGE_64BIT_LBA ...................................................................... libpayload/storage: Enable STORAGE_64BIT_LBA Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/libpayload/drivers/storage/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46534/1 diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index 268aa50..568282b 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -12,7 +12,7 @@ config STORAGE_64BIT_LBA bool "Use 64-bit integers to address sectors" depends on STORAGE - default n + default y help If this is selected, sectors will be addressed by an 64-bit integer. Select this to support LBA-48 for ATA drives. -- To view, visit https://review.coreboot.org/c/coreboot/+/46534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Gerrit-Change-Number: 46534 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/storage: Enable all AHCI controllers by default
by Felix Singer (Code Review) 19 Oct '20

19 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46533 ) Change subject: libpayload/storage: Enable all AHCI controllers by default ...................................................................... libpayload/storage: Enable all AHCI controllers by default Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/libpayload/drivers/storage/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46533/1 diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index fea52c8..268aa50 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -45,7 +45,7 @@ config STORAGE_AHCI_ONLY_TESTED bool "Only enable tested controllers" depends on STORAGE_AHCI - default y + default n help If this option is selected only AHCI controllers which are known to work will be used. -- To view, visit https://review.coreboot.org/c/coreboot/+/46533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Gerrit-Change-Number: 46533 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume
by Felix Held (Code Review) 19 Oct '20

19 Oct '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44398 ) Change subject: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume ...................................................................... soc/amd/picasso: Skip SmmInfo to PSP on S3 resume The PSP does not accept the SmmInfo command during a resume so remove the call. BUG=b:163017485 TEST=Run SST on trembyle, verify error message goes away BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/smi.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 125dde6..5822151 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -4,6 +4,7 @@ * Utilities for SMM setup */ +#include <acpi/acpi.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -19,5 +20,6 @@ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); - outb(APM_CNT_SMMINFO, APM_CNT); + if (!acpi_is_wakeup_s3()) + outb(APM_CNT_SMMINFO, APM_CNT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Gerrit-Change-Number: 44398 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/ifdtool: Enable CPU read for ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read for ME region ...................................................................... Patch Set 7: > Patch Set 6: Code-Review+1 > > Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. > > Can we please capture above lines in commit msg? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 15:34:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Enable CPU read for ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Hello build bot (Jenkins), Maulik V Vaghela, Stefan Reinauer, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#7). Change subject: util/ifdtool: Enable CPU read for ME region ...................................................................... util/ifdtool: Enable CPU read for ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch will enable read access to CSME region when locking. Also, we have enabled this change starting SKL/KBL. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Enable CPU read for ME region
by Maulik V Vaghela (Code Review) 19 Oct '20

19 Oct '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read for ME region ...................................................................... Patch Set 6: Code-Review+1 Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. Can we please capture above lines in commit msg? -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 15:11:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020