coreboot-gerrit October 2020

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Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Hello Maulik V Vaghela, Stefan Reinauer, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#4). Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... util/ifdtool: Enable CPU read of the ME region Using ifdtool after generating and flashing Coreboot image for locking RW access for JSL platform, 1. Flashrom should return success while erasing the SI_ME region and 2. After rebooting the DUT should boot into OS without any issues. But we see DUT is rebooting continuously after flashing the newly generated coreboot.bin.new This patch adds the code to enable CPU read for ME region after the ME lock operation. The security impact is taken care as the private data stored by CSE is all encrypted. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Thomas Heijligen (Code Review) 19 Oct '20

19 Oct '20

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 26 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 11:49:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/siemens/field_pg_m6: Add new mainboard
by Felix Singer (Code Review) 19 Oct '20

19 Oct '20

Hello Nico Huber, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39976 to review the following change. Change subject: [WIP] mb/siemens/field_pg_m6: Add new mainboard ...................................................................... [WIP] mb/siemens/field_pg_m6: Add new mainboard Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 14 files changed, 438 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/1 diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig new file mode 100644 index 0000000..fec610c --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + +config MAINBOARD_DIR + string + default "siemens/field_pg_m6" + +config MAINBOARD_FAMILY + string + default "Field PG M6" + +config MAINBOARD_PART_NUMBER + string + default "Field PG M6" + +config VARIANT_DIR + string + default "base" if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config MAX_CPUS + int + default 12 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0xb00000 + +endif diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig.name b/src/mainboard/siemens/field_pg_m6/Kconfig.name new file mode 100644 index 0000000..00cba93 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig.name @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +comment "Field PG M6" + +config BOARD_SIEMENS_FIELD_PG_M6_BASE + bool "-> Basic port" diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc new file mode 100644 index 0000000..8c563df --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/field_pg_m6/board_info.txt b/src/mainboard/siemens/field_pg_m6/board_info.txt new file mode 100644 index 0000000..cb5b428 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/siemens/field_pg_m6/dsdt.asl b/src/mainboard/siemens/field_pg_m6/dsdt.asl new file mode 100644 index 0000000..041fd4f --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/dsdt.asl @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/cannonlake/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads new file mode 100644 index 0000000..82da885 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads @@ -0,0 +1,26 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely + -- have a high-resolution display attached first, `Internal` last. + + ports : constant Port_List := + (DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c new file mode 100644 index 0000000..508ba22 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/mainboard.c @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <device/device.h> +#include <soc/gpio.h> +#include "variant.h" + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c new file mode 100644 index 0000000..380fc15 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/romstage.c @@ -0,0 +1,26 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct cnl_mb_cfg cfg = { + .spd = { + [0] = { READ_SMBUS, { 0x50 << 1 }}, + [2] = { READ_SMBUS, { 0x52 << 1 }}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, + }; + cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); + memupd->FspmConfig.EccSupport = 1; + memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; +} diff --git a/src/mainboard/siemens/field_pg_m6/variant.h b/src/mainboard/siemens/field_pg_m6/variant.h new file mode 100644 index 0000000..68f9afb --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variant.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#ifndef _VARIANT_H_ +#define _VARIANT_H_ + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc new file mode 100644 index 0000000..fdd7104 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt new file mode 100644 index 0000000..199a44e --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Field PG M6 diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt new file mode 100644 index 0000000..f79a6005 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt Binary files differ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb new file mode 100644 index 0000000..8fd83dd --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +chip soc/intel/cannonlake + + # TODO + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[16]" = "1" + + register "PcieClkSrcUsage[2]" = "0" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcUsage[7]" = "16" + + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[7]" = "7" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 x4 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c new file mode 100644 index 0000000..005d12c --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c @@ -0,0 +1,132 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * This file is part of the coreboot project. + */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO 0x0000003444000200 */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO 0x0000003544000300 */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO 0x0000003644000300 */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO 0x0000003a44000300 */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO 0x0000003b44000201 */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO 0x0000005044000300 */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO 0x0000005144000300 */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA 0x0000005884800402 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO 0x0000007544000201 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO 0x0000007644800100 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO 0x0000006d84000201 */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO 0x0000006e84800102 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* GPIO_RSVD_9 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_9, NONE), +/* GPIO_RSVD_10 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_10, NONE), +/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO 0x00000067c4000200 */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO 0x0000001c04000201 */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO 0x0000001d04000201 */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO 0x0000004884000102 */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO 0x0000005244800102 */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO 0x0000005744000201 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO 0x0000005944000201 */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO 0x0000002484000201 */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO 0x0000003584000201 */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO 0x0000003844800000 */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO 0x0000003944000200 */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK 0x0000004644000700 */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA 0x0000004744000702 */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP 0x0000003344000702 */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Gerrit-Change-Number: 39976 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

8 35

Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Nico Huber (Code Review) 19 Oct '20

19 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 26: Code-Review+2 +2 for things not authored by me -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 26 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 11:46:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Paul Menzel (Code Review) 19 Oct '20

19 Oct '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@8 PS3, Line 8: Please desribe the problem first. (flashrom fails to …) https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@9 PS3, Line 9: This patch adds the code to enable CPU read … for ME region https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@13 PS3, Line 13: return returns https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@14 PS3, Line 14: boot boots https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@15 PS3, Line 15: Drawlat EVT . Please remove the space before the dot/period. -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 11:36:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/rockchip/rk3288/include/soc/display.h: Add missing includes
by HAOUAS Elyes (Code Review) 19 Oct '20

19 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46329 ) Change subject: soc/rockchip/rk3288/include/soc/display.h: Add missing includes ...................................................................... soc/rockchip/rk3288/include/soc/display.h: Add missing includes Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/rockchip/rk3288/include/soc/display.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46329/1 diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h index 9883799..3cff4e9 100644 --- a/src/soc/rockchip/rk3288/include/soc/display.h +++ b/src/soc/rockchip/rk3288/include/soc/display.h @@ -3,6 +3,9 @@ #ifndef __SOC_ROCKCHIP_RK3288_DISPLAY_H__ #define __SOC_ROCKCHIP_RK3288_DISPLAY_H__ +#include <device/device.h> +#include <stdint.h> + /* * this bit select edp phy pll, this bit define different between * rk3288 and rk3399 in edp phy, so implement it in soc specific code -- To view, visit https://review.coreboot.org/c/coreboot/+/46329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b Gerrit-Change-Number: 46329 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros
by HAOUAS Elyes (Code Review) 19 Oct '20

19 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46330 ) Change subject: soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros ...................................................................... soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/rockchip/rk3288/gpio.c 1 file changed, 10 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46330/1 diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 885b419..ed09d02 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,21 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <gpio.h> +#include <soc/addressmap.h> #include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> struct rockchip_gpio_regs *gpio_port[] = { - (struct rockchip_gpio_regs *)0xff750000, - (struct rockchip_gpio_regs *)0xff780000, - (struct rockchip_gpio_regs *)0xff790000, - (struct rockchip_gpio_regs *)0xff7a0000, - (struct rockchip_gpio_regs *)0xff7b0000, - (struct rockchip_gpio_regs *)0xff7c0000, - (struct rockchip_gpio_regs *)0xff7d0000, - (struct rockchip_gpio_regs *)0xff7e0000, - (struct rockchip_gpio_regs *)0xff7f0000 + (struct rockchip_gpio_regs *)GPIO0_BASE, + (struct rockchip_gpio_regs *)GPIO1_BASE, + (struct rockchip_gpio_regs *)GPIO2_BASE, + (struct rockchip_gpio_regs *)GPIO3_BASE, + (struct rockchip_gpio_regs *)GPIO4_BASE, + (struct rockchip_gpio_regs *)GPIO5_BASE, + (struct rockchip_gpio_regs *)GPIO6_BASE, + (struct rockchip_gpio_regs *)GPIO7_BASE, + (struct rockchip_gpio_regs *)GPIO8_BASE }; #define PMU_GPIO_PORT 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/46330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b Gerrit-Change-Number: 46330 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/soc/samsung: Mouve common headers to "common/include/soc"
by HAOUAS Elyes (Code Review) 19 Oct '20

19 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46332 ) Change subject: src/soc/samsung: Mouve common headers to "common/include/soc" ...................................................................... src/soc/samsung: Mouve common headers to "common/include/soc" Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- R src/soc/samsung/common/include/soc/alternate_cbfs.h R src/soc/samsung/common/include/soc/dsim.h A src/soc/samsung/common/include/soc/i2c.h R src/soc/samsung/common/include/soc/i2s-regs.h R src/soc/samsung/common/include/soc/sysreg.h R src/soc/samsung/common/include/soc/tmu.h R src/soc/samsung/common/include/soc/trustzone.h R src/soc/samsung/common/include/soc/uart.h R src/soc/samsung/common/include/soc/wakeup.h D src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h D src/soc/samsung/exynos5250/include/soc/dsim.h D src/soc/samsung/exynos5250/include/soc/i2c.h D src/soc/samsung/exynos5250/include/soc/sysreg.h D src/soc/samsung/exynos5250/include/soc/tmu.h D src/soc/samsung/exynos5420/include/soc/i2c.h D src/soc/samsung/exynos5420/include/soc/i2s-regs.h D src/soc/samsung/exynos5420/include/soc/trustzone.h D src/soc/samsung/exynos5420/include/soc/uart.h D src/soc/samsung/exynos5420/include/soc/wakeup.h 19 files changed, 32 insertions(+), 538 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46332/1 diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/common/include/soc/alternate_cbfs.h similarity index 81% rename from src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h rename to src/soc/samsung/common/include/soc/alternate_cbfs.h index 4e49b84..63edc6a 100644 --- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/common/include/soc/alternate_cbfs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H -#define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H /* These are pointers to function pointers. Double indirection! */ static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; @@ -19,4 +19,4 @@ #define OM_STAT_SPI 0x14 #define OM_STAT_MASK 0x7f -#endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/common/include/soc/dsim.h similarity index 93% rename from src/soc/samsung/exynos5420/include/soc/dsim.h rename to src/soc/samsung/common/include/soc/dsim.h index b6b7ee9..541c72a 100644 --- a/src/soc/samsung/exynos5420/include/soc/dsim.h +++ b/src/soc/samsung/common/include/soc/dsim.h @@ -2,8 +2,8 @@ /* Register map for Exynos5 MIPI-DSIM */ -#ifndef CPU_SAMSUNG_EXYNOS5420_DSIM_H -#define CPU_SAMSUNG_EXYNOS5420_DSIM_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H /* DSIM register map */ struct exynos5_dsim { @@ -89,4 +89,4 @@ #define DSIM_STOP_STATE_CLK (1 << 8) #define DSIM_TX_READY_HS_CLK (1 << 10) -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H */ diff --git a/src/soc/samsung/common/include/soc/i2c.h b/src/soc/samsung/common/include/soc/i2c.h new file mode 100644 index 0000000..44feb6b --- /dev/null +++ b/src/soc/samsung/common/include/soc/i2c.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H + +void i2c_init(unsigned int bus, int speed, int slaveadd); + +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h b/src/soc/samsung/common/include/soc/i2s-regs.h similarity index 95% rename from src/soc/samsung/exynos5250/include/soc/i2s-regs.h rename to src/soc/samsung/common/include/soc/i2s-regs.h index 6b494da..012ca69 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h +++ b/src/soc/samsung/common/include/soc/i2s-regs.h @@ -2,8 +2,8 @@ /* Taken from the kernel code */ -#ifndef CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H -#define CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H #define I2SCON 0x0 #define I2SMOD 0x4 @@ -122,4 +122,4 @@ #define I2SSIZE_TRNMSK (0xffff) #define I2SSIZE_SHIFT (16) -#endif /* CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/sysreg.h b/src/soc/samsung/common/include/soc/sysreg.h similarity index 77% rename from src/soc/samsung/exynos5420/include/soc/sysreg.h rename to src/soc/samsung/common/include/soc/sysreg.h index 91ddf31..501d6d5 100644 --- a/src/soc/samsung/exynos5420/include/soc/sysreg.h +++ b/src/soc/samsung/common/include/soc/sysreg.h @@ -2,8 +2,8 @@ /* Register map for Exynos5 sysreg */ -#ifndef CPU_SAMSUNG_EXYNOS5420_SYSREG_H -#define CPU_SAMSUNG_EXYNOS5420_SYSREG_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H #include <soc/cpu.h> @@ -23,4 +23,4 @@ #define FIMDBYPASS_DISP1 (1 << 15) #define USB20_PHY_CFG_EN (1 << 0) -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/common/include/soc/tmu.h similarity index 95% rename from src/soc/samsung/exynos5420/include/soc/tmu.h rename to src/soc/samsung/common/include/soc/tmu.h index e65d69d..44996f6 100644 --- a/src/soc/samsung/exynos5420/include/soc/tmu.h +++ b/src/soc/samsung/common/include/soc/tmu.h @@ -2,8 +2,8 @@ /* EXYNOS - Thermal Management Unit */ -#ifndef CPU_SAMSUNG_EXYNOS5420_TMU_H -#define CPU_SAMSUNG_EXYNOS5420_TMU_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H struct tmu_reg { unsigned int triminfo; @@ -115,4 +115,4 @@ */ int tmu_init(struct tmu_info *info); -#endif /* CPU_SAMSUNG_EXYNOS5420_TMU_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/trustzone.h b/src/soc/samsung/common/include/soc/trustzone.h similarity index 88% rename from src/soc/samsung/exynos5250/include/soc/trustzone.h rename to src/soc/samsung/common/include/soc/trustzone.h index c867d08..c95e98d 100644 --- a/src/soc/samsung/exynos5250/include/soc/trustzone.h +++ b/src/soc/samsung/common/include/soc/trustzone.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H -#define CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H #include <stdint.h> @@ -62,4 +62,4 @@ void trustzone_init(void); -#endif /* CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/uart.h b/src/soc/samsung/common/include/soc/uart.h similarity index 74% rename from src/soc/samsung/exynos5250/include/soc/uart.h rename to src/soc/samsung/common/include/soc/uart.h index 0ac4ba1..b530e07 100644 --- a/src/soc/samsung/exynos5250/include/soc/uart.h +++ b/src/soc/samsung/common/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5250_UART_H -#define CPU_SAMSUNG_EXYNOS5250_UART_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H struct s5p_uart { unsigned int ulcon; @@ -21,4 +21,4 @@ }; check_member(s5p_uart, ubrdiv, 0x28); -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/wakeup.h b/src/soc/samsung/common/include/soc/wakeup.h similarity index 78% rename from src/soc/samsung/exynos5250/include/soc/wakeup.h rename to src/soc/samsung/common/include/soc/wakeup.h index 1d4f44a..bc67800 100644 --- a/src/soc/samsung/exynos5250/include/soc/wakeup.h +++ b/src/soc/samsung/common/include/soc/wakeup.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5250_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5250_WAKEUP_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,4 +23,4 @@ void wakeup(void); void wakeup_enable_uart(void); -#endif /* CPU_SAMSUNG_EXYNOS5250_WAKEUP_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h deleted file mode 100644 index b978e0c..0000000 --- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H -#define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H - -/* These are pointers to function pointers. Double indirection! */ -static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; -static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044; -static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048; -static void **const irom_spi_sf_read_ptr = (void **)0x02020058; -static void **const irom_load_image_from_usb_ptr = (void **)0x02020070; - -#define SECONDARY_BASE_BOOT_USB 0xfeed0002 -static u32 *const iram_secondary_base = (u32 *)0x02020018; - -/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ -#define OM_STAT_SDMMC 0x4 -#define OM_STAT_EMMC 0x8 -#define OM_STAT_SPI 0x14 -#define OM_STAT_MASK 0x7f - -#endif diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/exynos5250/include/soc/dsim.h deleted file mode 100644 index d851802..0000000 --- a/src/soc/samsung/exynos5250/include/soc/dsim.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Register map for Exynos5 MIPI-DSIM */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_DSIM_H -#define CPU_SAMSUNG_EXYNOS5250_DSIM_H - -/* DSIM register map */ -struct exynos5_dsim { - unsigned int status; - unsigned int swrst; - unsigned int clkctrl; - unsigned int timeout; - unsigned int config; - unsigned int escmode; - unsigned int mdresol; - unsigned int mvporch; - unsigned int mhporch; - unsigned int msync; - unsigned int sdresol; - unsigned int intsrc; - unsigned int intmsk; - unsigned int pkthdr; - unsigned int payload; - unsigned int rxfifo; - unsigned int res1; - unsigned int fifoctrl; - unsigned int res2; - unsigned int pllctrl; - unsigned int plltmr; - unsigned int phyacchr; - unsigned int phyacchr1; -}; -check_member(exynos5_dsim, phyacchr1, 0x54); - -#define ENABLE 1 -#define DISABLE 0 - -#define DSIM_SWRST (1 << 0) -#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5) -#define DATA_LANE_0_EN (1 << 0) -#define DATA_LANE_1_EN (1 << 1) -#define DATA_LANE_2_EN (1 << 2) -#define DATA_LANE_3_EN (1 << 3) -#define CLK_LANE_EN (1 << 4) -#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \ - DATA_LANE_1_EN | \ - DATA_LANE_2_EN | \ - DATA_LANE_3_EN -#define MAIN_PIX_FORMAT_OFFSET 12 -#define RGB_565_16_BIT 0x4 -#define VIDEO_MODE (1 << 25) -#define BURST_MODE (1 << 26) - -#define DSIM_PHYACCHR_AFC_EN (1 << 14) -#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 - -#define DSIM_PLLCTRL_PMS_OFFSET 1 -#define DSIM_FREQ_BAND_OFFSET 24 - -#define LANE_ESC_CLK_EN_ALL (0x1f << 19) -#define BYTE_CLK_EN (1 << 24) -#define DSIM_ESC_CLK_EN (1 << 28) -#define TXREQUEST_HS_CLK_ON (1 << 31) - -#define LP_MODE_ENABLE (1 << 7) -#define STOP_STATE_CNT_OFFSET 21 - -#define MAIN_VBP_OFFSET 0 -#define STABLE_VFP_OFFSET 16 -#define CMD_ALLOW_OFFSET 28 - -#define MAIN_HBP_OFFSET 0 -#define MAIN_HFP_OFFSET 16 - -#define MAIN_HSA_OFFSET 0 -#define MAIN_VSA_OFFSET 22 - -#define MAIN_STANDBY (1 << 31) -#define MAIN_VRESOL_OFFSET 16 -#define MAIN_HRESOL_OFFSET 0 - -#define SFR_FIFO_EMPTY (1 << 29) - -#define DSIM_PLL_EN_SHIFT (1 << 23) -#define PLL_STABLE (1 << 31) - -#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) - -#endif diff --git a/src/soc/samsung/exynos5250/include/soc/i2c.h b/src/soc/samsung/exynos5250/include/soc/i2c.h deleted file mode 100644 index 76c4cbb..0000000 --- a/src/soc/samsung/exynos5250/include/soc/i2c.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H -#define CPU_SAMSUNG_EXYNOS5250_I2C_H - -void i2c_init(unsigned int bus, int speed, int slaveadd); - -#endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/sysreg.h b/src/soc/samsung/exynos5250/include/soc/sysreg.h deleted file mode 100644 index 3219264..0000000 --- a/src/soc/samsung/exynos5250/include/soc/sysreg.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Register map for Exynos5 sysreg */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_SYSREG_H -#define CPU_SAMSUNG_EXYNOS5250_SYSREG_H - -#include <soc/cpu.h> - -/* sysreg map */ -struct exynos5_sysreg { - /* Add registers as and when required */ - unsigned char res1[0x214]; - unsigned int disp1blk_cfg; - unsigned char res2[0x18]; - unsigned int usb20_phy_cfg; -}; -check_member(exynos5_sysreg, usb20_phy_cfg, 0x230); - -static struct exynos5_sysreg * const exynos_sysreg = - (void *)EXYNOS5_SYSREG_BASE; - -#define FIMDBYPASS_DISP1 (1 << 15) -#define USB20_PHY_CFG_EN (1 << 0) - -#endif diff --git a/src/soc/samsung/exynos5250/include/soc/tmu.h b/src/soc/samsung/exynos5250/include/soc/tmu.h deleted file mode 100644 index cb7e472..0000000 --- a/src/soc/samsung/exynos5250/include/soc/tmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* EXYNOS - Thermal Management Unit */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_TMU_H -#define CPU_SAMSUNG_EXYNOS5250_TMU_H - -struct tmu_reg { - unsigned int triminfo; - unsigned int rsvd1; - unsigned int rsvd2; - unsigned int rsvd3; - unsigned int rsvd4; - unsigned int triminfo_control; - unsigned int rsvd5; - unsigned int rsvd6; - unsigned int tmu_control; - unsigned int rsvd7; - unsigned int tmu_status; - unsigned int sampling_internal; - unsigned int counter_value0; - unsigned int counter_value1; - unsigned int rsvd8; - unsigned int rsvd9; - unsigned int current_temp; - unsigned int rsvd10; - unsigned int rsvd11; - unsigned int rsvd12; - unsigned int threshold_temp_rise; - unsigned int threshold_temp_fall; - unsigned int rsvd13; - unsigned int rsvd14; - unsigned int past_temp3_0; - unsigned int past_temp7_4; - unsigned int past_temp11_8; - unsigned int past_temp15_12; - unsigned int inten; - unsigned int intstat; - unsigned int intclear; - unsigned int rsvd15; - unsigned int emul_con; -}; -check_member(tmu_reg, emul_con, 0x80); - -enum tmu_status_t { - TMU_STATUS_INIT = 0, - TMU_STATUS_NORMAL, - TMU_STATUS_WARNING, - TMU_STATUS_TRIPPED, -}; - -/* Temperature threshold values for various thermal events */ -struct temperature_params { - /* minimum value in temperature code range */ - unsigned int min_val; - /* maximum value in temperature code range */ - unsigned int max_val; - /* temperature threshold to start warning */ - unsigned int start_warning; - /* temperature threshold CPU tripping */ - unsigned int start_tripping; - /* temperature threshold for HW tripping */ - unsigned int hardware_tripping; -}; - -/* Pre-defined values and thresholds for calibration of current temperature */ -struct tmu_data { - /* pre-defined temperature thresholds */ - struct temperature_params ts; - /* pre-defined efuse range minimum value */ - unsigned int efuse_min_value; - /* pre-defined efuse value for temperature calibration */ - unsigned int efuse_value; - /* pre-defined efuse range maximum value */ - unsigned int efuse_max_value; - /* current temperature sensing slope */ - unsigned int slope; -}; - -/* TMU device specific details and status */ -struct tmu_info { - /* base Address for the TMU */ - unsigned int tmu_base; - /* mux Address for the TMU */ - int tmu_mux; - /* pre-defined values for calibration and thresholds */ - struct tmu_data data; - /* value required for triminfo_25 calibration */ - unsigned int te1; - /* value required for triminfo_85 calibration */ - unsigned int te2; - /* TMU DC value for threshold calculation */ - int dc_value; - /* enum value indicating status of the TMU */ - int tmu_state; -}; - -extern struct tmu_info *tmu_info; - -/* - * Monitors status of the TMU device and exynos temperature - * - * @info pointer to TMU info struct - * @temp pointer to the current temperature value - * @return enum tmu_status_t value, code indicating event to execute - * and -1 on error - */ -enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp); - -/* - * Initialize TMU device - * - * @info pointer to TMU info struct - * @return int value, 0 for success - */ -int tmu_init(struct tmu_info *info); - -#endif /* CPU_SAMSUNG_EXYNOS5250_TMU_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h deleted file mode 100644 index 8b2f019..0000000 --- a/src/soc/samsung/exynos5420/include/soc/i2c.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H -#define CPU_SAMSUNG_EXYNOS5420_I2C_H - -void i2c_init(unsigned int bus, int speed, int slaveadd); - -#endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h deleted file mode 100644 index 696eb2f..0000000 --- a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Taken from the kernel code */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H -#define CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H - -#define I2SCON 0x0 -#define I2SMOD 0x4 -#define I2SFIC 0x8 -#define I2SPSR 0xc -#define I2STXD 0x10 -#define I2SRXD 0x14 -#define I2SFICS 0x18 -#define I2STXDS 0x1c -#define I2SAHB 0x20 -#define I2SSTR0 0x24 -#define I2SSIZE 0x28 -#define I2STRNCNT 0x2c -#define I2SLVL0ADDR 0x30 -#define I2SLVL1ADDR 0x34 -#define I2SLVL2ADDR 0x38 -#define I2SLVL3ADDR 0x3c - -#define CON_RSTCLR (1 << 31) -#define CON_FRXOFSTATUS (1 << 26) -#define CON_FRXORINTEN (1 << 25) -#define CON_FTXSURSTAT (1 << 24) -#define CON_FTXSURINTEN (1 << 23) -#define CON_TXSDMA_PAUSE (1 << 20) -#define CON_TXSDMA_ACTIVE (1 << 18) - -#define CON_FTXURSTATUS (1 << 17) -#define CON_FTXURINTEN (1 << 16) -#define CON_TXFIFO2_EMPTY (1 << 15) -#define CON_TXFIFO1_EMPTY (1 << 14) -#define CON_TXFIFO2_FULL (1 << 13) -#define CON_TXFIFO1_FULL (1 << 12) - -#define CON_LRINDEX (1 << 11) -#define CON_TXFIFO_EMPTY (1 << 10) -#define CON_RXFIFO_EMPTY (1 << 9) -#define CON_TXFIFO_FULL (1 << 8) -#define CON_RXFIFO_FULL (1 << 7) -#define CON_TXDMA_PAUSE (1 << 6) -#define CON_RXDMA_PAUSE (1 << 5) -#define CON_TXCH_PAUSE (1 << 4) -#define CON_RXCH_PAUSE (1 << 3) -#define CON_TXDMA_ACTIVE (1 << 2) -#define CON_RXDMA_ACTIVE (1 << 1) -#define CON_ACTIVE (1 << 0) - -#define MOD_OPCLK_CDCLK_OUT (0 << 30) -#define MOD_OPCLK_CDCLK_IN (1 << 30) -#define MOD_OPCLK_BCLK_OUT (2 << 30) -#define MOD_OPCLK_PCLK (3 << 30) -#define MOD_OPCLK_MASK (3 << 30) -#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ - -#define MOD_BLCS_SHIFT 26 -#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) -#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) -#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) -#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) - -#define MOD_BLCP_SHIFT 24 -#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) -#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) -#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) -#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) - -#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ -#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ -#define MOD_C1DD_HHALF (1 << 19) -#define MOD_C1DD_LHALF (1 << 18) -#define MOD_DC2_EN (1 << 17) -#define MOD_DC1_EN (1 << 16) -#define MOD_BLC_16BIT (0 << 13) -#define MOD_BLC_8BIT (1 << 13) -#define MOD_BLC_24BIT (2 << 13) -#define MOD_BLC_MASK (3 << 13) - -#define MOD_IMS_SYSMUX (1 << 10) -#define MOD_SLAVE (1 << 11) -#define MOD_TXONLY (0 << 8) -#define MOD_RXONLY (1 << 8) -#define MOD_TXRX (2 << 8) -#define MOD_MASK (3 << 8) -#define MOD_LR_LLOW (0 << 7) -#define MOD_LR_RLOW (1 << 7) -#define MOD_SDF_IIS (0 << 5) -#define MOD_SDF_MSB (1 << 5) -#define MOD_SDF_LSB (2 << 5) -#define MOD_SDF_MASK (3 << 5) -#define MOD_RCLK_256FS (0 << 3) -#define MOD_RCLK_512FS (1 << 3) -#define MOD_RCLK_384FS (2 << 3) -#define MOD_RCLK_768FS (3 << 3) -#define MOD_RCLK_MASK (3 << 3) -#define MOD_BCLK_32FS (0 << 1) -#define MOD_BCLK_48FS (1 << 1) -#define MOD_BCLK_16FS (2 << 1) -#define MOD_BCLK_24FS (3 << 1) -#define MOD_BCLK_MASK (3 << 1) -#define MOD_8BIT (1 << 0) - -#define MOD_CDCLKCON (1 << 12) - -#define PSR_PSREN (1 << 15) - -#define FIC_TXFLUSH (1 << 15) -#define FIC_RXFLUSH (1 << 7) - -#define AHB_INTENLVL0 (1 << 24) -#define AHB_LVL0INT (1 << 20) -#define AHB_CLRLVL0INT (1 << 16) -#define AHB_DMARLD (1 << 5) -#define AHB_INTMASK (1 << 3) -#define AHB_DMAEN (1 << 0) -#define AHB_LVLINTMASK (0xf << 20) - -#define I2SSIZE_TRNMSK (0xffff) -#define I2SSIZE_SHIFT (16) - -#endif /* CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/trustzone.h b/src/soc/samsung/exynos5420/include/soc/trustzone.h deleted file mode 100644 index 21f8a0e..0000000 --- a/src/soc/samsung/exynos5420/include/soc/trustzone.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H -#define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H - -#include <stdint.h> - -/* Distance between each Trust Zone PC register set */ -#define TZPC_BASE_OFFSET 0x10000 -/* TZPC : Register Offsets */ -#define TZPC0_BASE 0x10100000 -#define TZPC1_BASE 0x10110000 -#define TZPC2_BASE 0x10120000 -#define TZPC3_BASE 0x10130000 -#define TZPC4_BASE 0x10140000 -#define TZPC5_BASE 0x10150000 -#define TZPC6_BASE 0x10160000 -#define TZPC7_BASE 0x10170000 -#define TZPC8_BASE 0x10180000 -#define TZPC9_BASE 0x10190000 -#define TZPC10_BASE 0x100E0000 -#define TZPC11_BASE 0x100F0000 - -/* - * TZPC Register Value : - * R0SIZE: 0x0 : Size of secured ram - */ -#define R0SIZE 0x0 - -/* - * TZPC Decode Protection Register Value : - * DECPROTXSET: 0xFF : Set Decode region to non-secure - */ -#define DECPROTXSET 0xFF - -struct exynos_tzpc { - u32 r0size; - u8 res1[0x7FC]; - u32 decprot0stat; - u32 decprot0set; - u32 decprot0clr; - u32 decprot1stat; - u32 decprot1set; - u32 decprot1clr; - u32 decprot2stat; - u32 decprot2set; - u32 decprot2clr; - u32 decprot3stat; - u32 decprot3set; - u32 decprot3clr; - u8 res2[0x7B0]; - u32 periphid0; - u32 periphid1; - u32 periphid2; - u32 periphid3; - u32 pcellid0; - u32 pcellid1; - u32 pcellid2; - u32 pcellid3; -}; -check_member(exynos_tzpc, pcellid3, 0xffc); - -void trustzone_init(void); - -#endif /* CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/uart.h b/src/soc/samsung/exynos5420/include/soc/uart.h deleted file mode 100644 index de9975c..0000000 --- a/src/soc/samsung/exynos5420/include/soc/uart.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_UART_H -#define CPU_SAMSUNG_EXYNOS5420_UART_H - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - unsigned char res3[0xffd0]; -}; -check_member(s5p_uart, ubrdiv, 0x28); - -#endif diff --git a/src/soc/samsung/exynos5420/include/soc/wakeup.h b/src/soc/samsung/exynos5420/include/soc/wakeup.h deleted file mode 100644 index a9b8fc5..0000000 --- a/src/soc/samsung/exynos5420/include/soc/wakeup.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5420_WAKEUP_H - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -enum { - // A normal boot (not suspend/resume) - IS_NOT_WAKEUP, - // A wake up event that can be resumed any time - WAKEUP_DIRECT, - // A wake up event that must be resumed only after - // clock and memory controllers are re-initialized - WAKEUP_NEED_CLOCK_RESET, -}; - -int wakeup_need_reset(void); -int get_wakeup_state(void); -void wakeup(void); -void wakeup_enable_uart(void); - -#endif /* CPU_SAMSUNG_EXYNOS5420_WAKEUP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Gerrit-Change-Number: 46332 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/octopus/variants/ampton: Add G2Touch touchscreen support
by James Chao (Code Review) 19 Oct '20

19 Oct '20

James Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46344 ) Change subject: mb/google/octopus/variants/ampton: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/ampton: Add G2Touch touchscreen support BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao <james_chao(a)asus.corp-partner.google.com> Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46344/1 diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 10ff7d7..3d14bea 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -121,6 +121,20 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Gerrit-Change-Number: 46344 Gerrit-PatchSet: 1 Gerrit-Owner: James Chao <james_chao(a)asus.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/*: drop useless XTAL shutdown qualification code
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46016 ) Change subject: soc/intel/*: drop useless XTAL shutdown qualification code ...................................................................... soc/intel/*: drop useless XTAL shutdown qualification code The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/finalize.c 9 files changed, 5 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 24dbbd6..b18d72b 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -64,10 +64,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 9eb9cbe..6ef43b9 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -73,16 +73,11 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - if (config->s0ix_enable) { - /* Disable XTAL shutdown qualification for low power idle. */ - pmc_ignore_xtal_shutdown(); - - if (config->cppmvric2_adsposcdis) { - /* Enable Audio DSP OSC qualification for S0ix */ - reg32 = read32(pmcbase + CPPMVRIC2); - reg32 &= ~ADSPOSCDIS; - write32(pmcbase + CPPMVRIC2, reg32); - } + if (config->s0ix_enable && config->cppmvric2_adsposcdis) { + /* Enable Audio DSP OSC qualification for S0ix */ + reg32 = read32(pmcbase + CPPMVRIC2); + reg32 &= ~ADSPOSCDIS; + write32(pmcbase + CPPMVRIC2, reg32); } pch_handle_sideband(config); diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fa063f2..2acc275 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -232,7 +232,4 @@ /* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ void pmc_disable_acpi_timer(void); -/* Disable XTAL shutdown qualification for low power idle. */ -void pmc_ignore_xtal_shutdown(void); - #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 8825bbe..a5dff2d 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -708,11 +708,4 @@ setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } - -void pmc_ignore_xtal_shutdown(void) -{ - uint8_t *pmcbase = pmc_mmio_regs(); - - setbits8(pmcbase + CPPMVRIC, XTALSDQDIS); -} #endif /* PMC_LOW_POWER_MODE_PROGRAM */ diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index bae8bcf..a1cfd8b 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -45,10 +45,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 363f579..395bd39 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -70,10 +70,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 1badad3..61b8e33 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -63,10 +63,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index ff32189..9edc7a2 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -73,10 +73,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 2cc9671..44e6806 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -51,10 +51,6 @@ if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pmc_clear_pmcon_sts(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Gerrit-Change-Number: 46016 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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