coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/kukui: Support SKU from camera EEPROM
by Yu-Ping Wu (Code Review) 19 Oct '20

19 Oct '20

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45811 to review the following change. Change subject: mb/google/kukui: Support SKU from camera EEPROM ...................................................................... mb/google/kukui: Support SKU from camera EEPROM To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/boardid.c 2 files changed, 102 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45811/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 532712a..7e065a3 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += sdram_params/ subdirs-y += panel_params/ -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += reset.c diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 548f36b..f8219fb 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -3,8 +3,14 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> -#include <soc/auxadc.h> +#include <delay.h> +#include <device/i2c_simple.h> #include <ec/google/chromeec/ec.h> +#include <soc/auxadc.h> +#include <soc/i2c.h> +#include <soc/pmic_wrap_common.h> +#include <string.h> +#include <vendorcode/google/chromeos/camera.h> /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 @@ -72,6 +78,97 @@ return id; } +static uint8_t eeprom_random_read(uint8_t bus, uint8_t slave, uint16_t offset, + uint8_t *data, uint16_t len) +{ + struct i2c_msg seg[2]; + uint8_t address[2]; + + address[0] = offset >> 8; + address[1] = offset & 0xff; + + seg[0].flags = 0; + seg[0].slave = slave; + seg[0].buf = address; + seg[0].len = sizeof(address); + seg[1].flags = I2C_M_RD; + seg[1].slave = slave; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + +/* Regulator for world facing camera. */ +#define PMIC_LDO_VCAMIO_CON0 0x1cb0 + +#define CROS_CAMERA_INFO_OFFSET 0x1f80 +#define MT8183_FORMAT 0x8183 +#define KODAMA_REVISION 0x00c7 + +/* Returns the ID for world facing camera. */ +static uint8_t wfc_id(void) +{ + if (!CONFIG(BOARD_GOOGLE_KODAMA)) + return 0; + + int i, ret; + uint8_t bus = 2; + uint8_t dev_addr = 0x50; /* at24c32/64 device address */ + + struct cros_camera_info data = {0}; + + const uint16_t sensor_models[] = { + [0] = 0x5965, /* OV5965 */ + [1] = 0x5035, /* GC5035 */ + }; + + mtk_i2c_bus_init(bus); + + /* Turn on camera sensor EEPROM */ + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x1); + udelay(270); + + ret = eeprom_random_read(bus, dev_addr, CROS_CAMERA_INFO_OFFSET, + (uint8_t *)&data, sizeof(data)); + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x0); + + if (ret) { + printk(BIOS_ERR, + "Failed to read from EEPROM; using default WFC id 0\n"); + return 0; + } + + if (check_cros_camera_info(&data)) { + printk(BIOS_ERR, + "Failed to check camera info; using default WFC id 0\n"); + return 0; + } + + if (data.data_format != MT8183_FORMAT) { + printk(BIOS_ERR, "Incompatible camera format: %#04x\n", + data.data_format); + return 0; + } + if (data.module_revision != KODAMA_REVISION) { + printk(BIOS_ERR, "Incompatible module revision: %#04x\n", + data.module_revision); + return 0; + } + + printk(BIOS_DEBUG, "Camera sensor model: %#04x\n", data.sensor_model); + + for (i = 0; i < ARRAY_SIZE(sensor_models); i++) { + if (data.sensor_model == sensor_models[i]) { + printk(BIOS_INFO, "Detected WFC id: %d\n", i); + return i; + } + } + + printk(BIOS_WARNING, "Unknown WFC id; using default id 0\n"); + return 0; +} + /* board_id is provided by ec/google/chromeec/ec_boardid.c */ uint32_t sku_id(void) @@ -98,11 +195,14 @@ /* * The SKU (later used for device tree matching) is combined from: + * World facing camera (WFC) ID. * ADC2[4bit/H] = straps on LCD module (type of panel). * ADC4[4bit/L] = SKU ID from board straps. */ - cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | + cached_sku_id = (wfc_id() << 8 | + get_adc_index(LCM_ID_CHANNEL) << 4 | get_adc_index(SKU_ID_CHANNEL)); + return cached_sku_id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Gerrit-Change-Number: 45811 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/google/chromeos: Add camera info
by Yu-Ping Wu (Code Review) 19 Oct '20

19 Oct '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46042 ) Change subject: vendorcode/google/chromeos: Add camera info ...................................................................... vendorcode/google/chromeos: Add camera info Add cros_camera_info struct for camera information, and check_cros_camera_info() for checking the magic, CRC and version. BUG=b:144820097 TEST=emerge-kukui coreboot BRANCH=kukui Change-Id: I1215fec76643b0cf7e09433e1190e8bd387e6953 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/camera.c A src/vendorcode/google/chromeos/camera.h 3 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46042/1 diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17236d..be6240b 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -4,6 +4,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +ramstage-y += camera.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c diff --git a/src/vendorcode/google/chromeos/camera.c b/src/vendorcode/google/chromeos/camera.c new file mode 100644 index 0000000..71e28f6 --- /dev/null +++ b/src/vendorcode/google/chromeos/camera.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <crc_byte.h> +#include <string.h> + +#include "camera.h" + +int check_cros_camera_info(const struct cros_camera_info *info) +{ + if (memcmp(info->magic, CROS_CAMERA_INFO_MAGIC, sizeof(info->magic))) { + printk(BIOS_ERR, "Invalid magic in camera info\n"); + return -1; + } + + const uint8_t *ptr = (void *)&info->version; + uint16_t crc16 = 0; + while (ptr < (uint8_t *)info + sizeof(struct cros_camera_info)) + crc16 = crc16_byte(crc16, *ptr++); + + if (info->crc16 != crc16) { + printk(BIOS_ERR, "Incorrect CRC16: expected %#06x, got %#06x\n", + crc16, info->crc16); + return -1; + } + + if (info->version != CROS_CAMERA_INFO_VERSION) { + printk(BIOS_ERR, "Unknown camera info version: %u\n", + info->version); + return -1; + } + if (info->size < CROS_CAMERA_INFO_SIZE_MIN) { + printk(BIOS_ERR, "Size of camera info is too small: %u\n", + info->size); + return -1; + } + + return 0; +} diff --git a/src/vendorcode/google/chromeos/camera.h b/src/vendorcode/google/chromeos/camera.h new file mode 100644 index 0000000..36b7646 --- /dev/null +++ b/src/vendorcode/google/chromeos/camera.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H +#define __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H + +#include <stdint.h> + +#define CROS_CAMERA_INFO_MAGIC "CrOS" +#define CROS_CAMERA_INFO_VERSION 1 +#define CROS_CAMERA_INFO_SIZE_MIN 0x0a + +struct cros_camera_info { + uint8_t magic[4]; /* CROS_CAMERA_INFO_MAGIC */ + uint16_t crc16; + uint8_t version; + uint8_t size; + uint16_t data_format; + uint16_t module_revision; + uint8_t module_vendor[2]; + uint8_t sensor_vendor[2]; + uint16_t sensor_model; +}; + +/* Returns 0 on success, non-zero on errors. */ +int check_cros_camera_info(const struct cros_camera_info *info); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1215fec76643b0cf7e09433e1190e8bd387e6953 Gerrit-Change-Number: 46042 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/elemi: Add memory.c for DDR4
by Chen Wisley (Code Review) 19 Oct '20

19 Oct '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46378 ) Change subject: mb/google/volteer/elemi: Add memory.c for DDR4 ...................................................................... mb/google/volteer/elemi: Add memory.c for DDR4 Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 --- A src/mainboard/google/volteer/variants/elemi/Makefile.inc A src/mainboard/google/volteer/variants/elemi/memory.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46378/1 diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc new file mode 100644 index 0000000..9064208 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c new file mode 100644 index 0000000..577734d --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg eldrid_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &eldrid_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Gerrit-Change-Number: 46378 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_skl: Clean up FSP-M RCOMP settings
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46252 ) Change subject: mb/purism/librem_skl: Clean up FSP-M RCOMP settings ...................................................................... mb/purism/librem_skl: Clean up FSP-M RCOMP settings There's no need to use static functions to fill these settings in. Also, add missing include for <stdint.h> and constify the `mem_cfg` pointer. Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_skl/romstage.c 1 file changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46252/1 diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 4982836..698cb37 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -3,37 +3,30 @@ #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> +#include <stdint.h> #include <string.h> -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; + const u16 rcomp_resistors[3] = { 121, 81, 100 }; + + const u16 rcomp_targets[5] = { 100, 40, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50 }, }; - mem_cfg = &mupd->FspmConfig; + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); get_spd_smbus(&blk); dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; -- To view, visit https://review.coreboot.org/c/coreboot/+/46252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Gerrit-Change-Number: 46252 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: update dptc stapm time
by John Su (Code Review) 19 Oct '20

19 Oct '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46048 ) Change subject: mb/google/zork/var/vilboz: update dptc stapm time ...................................................................... mb/google/zork/var/vilboz: update dptc stapm time Update dptc setting: Stapm_time_constant 1400 BRANCH=zork TEST=emerge coreboot and check "Stapm_time_constant" Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46048/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 3d9ff7c..73db6fd 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -13,7 +13,7 @@ register "slow_ppt_limit" = "6000" # mW register "fast_ppt_limit" = "9000" # mW register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "2500" # second + register "stapm_time_constant" = "1400" # second register "sustained_power_limit" = "4800" # mW # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/46048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd Gerrit-Change-Number: 46048 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Reflow long lines
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46072 ) Change subject: soc/intel/tigerlake: Reflow long lines ...................................................................... soc/intel/tigerlake: Reflow long lines Use the 96 character limit. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..7e830f0 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -441,12 +441,10 @@ { switch (board_cfg->mem_type) { case MEMTYPE_DDR4: - meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, - half_populated); + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, half_populated); break; case MEMTYPE_LPDDR4X: - meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, - half_populated); + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, half_populated); break; default: die("Unsupported memory type = %d!\n", board_cfg->mem_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/46072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Gerrit-Change-Number: 46072 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Reflow long lines
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has uploaded a new patch set (#4) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46072 ) Change subject: soc/intel/tigerlake: Reflow long lines ...................................................................... soc/intel/tigerlake: Reflow long lines Use the 96 character limit. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46072/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Gerrit-Change-Number: 46072 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb
by Marc Jones (Code Review) 19 Oct '20

19 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46309 ) Change subject: soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb ...................................................................... soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb platform_fsp_silicon_init_params_cb is called by the fsp driver and calls mainboard_silicon_init_params which sets the mainboard PCH GPIOs. Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/46309/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index f69797a..6d2dfba 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -489,9 +489,11 @@ DEV_FUNC_EXIT(dev); } +/* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { - /* not implemented yet */ + + mainboard_silicon_init_params(silupd); } #if CONFIG(HAVE_ACPI_TABLES) -- To view, visit https://review.coreboot.org/c/coreboot/+/46309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Gerrit-Change-Number: 46309 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: allow to override chip-wrapped devices
by Michael Niewöhner (Code Review) 18 Oct '20

18 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Duncan Laurie, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46531 to look at the new patch set (#7). Change subject: util/sconfig: allow to override chip-wrapped devices ...................................................................... util/sconfig: allow to override chip-wrapped devices Currently, when a overridetree disables a device wrapped by a chip driver in the base tree, without having the same wrapping chip, sconfig mistakenly creates two instances of the same device. This leads to a conflict. The following example shows that: base tree: chip soc/intel/whateverlake device domain 0 on chip drivers/wifi/generic device pci 14.3 on end end end end overridetree: ... device pci 14.3 off end ... The static.[ch] then contains two declarations of the same device: extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_14_3; ... extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_14_3; The same problem appears with the newly introduced chipset devicetrees, that only include the device without chip driver. An overridetree wrapping such device by a chip driver - which the same example above with swapped base and overridetree represents - will lead to the same problem. To cover such use cases, move the match check for chip drivers into the device update procedure and override the base chip accordingly if the chip driver does not match. If the chip driver matches, there is no change to the original behaviour. Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M util/sconfig/main.c 1 file changed, 37 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46531/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Gerrit-Change-Number: 46531 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/sconfig: allow to override chip-wrapped devices
by build bot (Jenkins) (Code Review) 18 Oct '20

18 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46531 ) Change subject: util/sconfig: allow to override chip-wrapped devices ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/46531/6/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/46531/6/util/sconfig/main.c@1595 PS6, Line 1595: if (chip_match(base_dev, override_dev)) that open brace { should be on the previous line https://review.coreboot.org/c/coreboot/+/46531/6/util/sconfig/main.c@1618 PS6, Line 1618: * Update base_chip_instance member in chip instance of override tree to forward it to line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/46531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6364b3a6e1804a23503f42c66c5001e42f911270 Gerrit-Change-Number: 46531 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Oct 2020 00:45:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020