coreboot-gerrit October 2020

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Change in coreboot[master]: Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency"
by Rob Barnes (Code Review) 19 Oct '20

19 Oct '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45004 to review the following change. Change subject: Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency" ...................................................................... Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency" This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51. Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible. Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c --- M src/mainboard/google/zork/variants/dalboz/overridetree.cb 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45004/1 diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index e5608d9..1ddb17b 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -37,12 +37,6 @@ .early_init = true, }" - register "emmc_config" = "{ - .timing = SD_EMMC_EMMC_HS400, - .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, - .init_khz_preset = 400, - }" - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c Gerrit-Change-Number: 45004 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer The camera sensor component chosen for UFC and WFC have an address conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also configure the GPIO that is used as select line. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/waddledee/Makefile.inc A src/mainboard/google/dedede/variants/waddledee/gpio.c M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 4 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2892dd1..377702d 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -4,6 +4,7 @@ select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index eda535c..93f34f8 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -2,4 +2,5 @@ romstage-y += memory.c +ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c new file mode 100644 index 0000000..0905e8f --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* E5 : AP_SUB_IO_2 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 22a08a0..b67b870 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -119,6 +119,20 @@ device i2c 0x5d on end end end # I2C 2 + device pci 15.3 on + chip drivers/i2c/gpiomux/mux + register "mux_gpio_count" = "1" + register "mux_gpio[0]" = "ACPI_GPIO_OUTPUT(GPP_E5)" + device generic 0 on + chip drivers/i2c/gpiomux/bus + device generic 0 on end # I2C Mux Bus 0 + end + chip drivers/i2c/gpiomux/bus + device generic 1 on end # I2C Mux Bus 1 + end + end # I2C MUX + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/gpiomux: Add chip driver for multiplexed I2C bus
by Karthik Ramasubramanian (Code Review) 19 Oct '20

19 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46144 ) Change subject: drivers/i2c/gpiomux: Add chip driver for multiplexed I2C bus ...................................................................... drivers/i2c/gpiomux: Add chip driver for multiplexed I2C bus This chip driver adds ACPI identifiers for multiplexed I2C bus that are selected using GPIO. The multiplexed bus device defines the address to select the I2C lines. BUG=b:169444894 TEST=Build and boot to OS in waddledee. Ensure that the ACPI identifiers are added in appropriate context. Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, Zero) // _ADR: Address } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA1) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, One) // _ADR: Address } } Change-Id: If8b983bc8ce212ce05fe6b7f01a6d9092468e582 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/i2c/gpiomux/Makefile.inc A src/drivers/i2c/gpiomux/bus/Makefile.inc A src/drivers/i2c/gpiomux/bus/bus.c A src/drivers/i2c/gpiomux/bus/chip.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46144/1 diff --git a/src/drivers/i2c/gpiomux/Makefile.inc b/src/drivers/i2c/gpiomux/Makefile.inc index fec8d5b..5c328cb 100644 --- a/src/drivers/i2c/gpiomux/Makefile.inc +++ b/src/drivers/i2c/gpiomux/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus diff --git a/src/drivers/i2c/gpiomux/bus/Makefile.inc b/src/drivers/i2c/gpiomux/bus/Makefile.inc new file mode 100644 index 0000000..1c462dc --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus.c diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c new file mode 100644 index 0000000..96763e9 --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <stdlib.h> +#include <string.h> +#include "chip.h" + +static const char *i2c_gpiomux_bus_acpi_name(const struct device *dev) +{ + struct drivers_i2c_gpiomux_bus_config *config = dev->chip_info; + char *name; + + if (config->name) + return config->name; + + name = malloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MXA%01.1X", dev->path.generic.id); + name[ACPI_NAME_BUFFER_SIZE - 1] = '\0'; + config->name = name; + return name; +} + +static void i2c_gpiomux_bus_fill_ssdt_generator(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_name_integer("_ADR", dev->path.generic.id); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_bus_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_bus_fill_ssdt_generator, +}; + +static void i2c_gpiomux_bus_enable(struct device *dev) +{ + struct drivers_i2c_gpiomux_bus_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &i2c_gpiomux_bus_ops; +} + +struct chip_operations drivers_i2c_gpiomux_bus_ops = { + CHIP_NAME("I2C GPIO MUX Bus Device") + .enable_dev = i2c_gpiomux_bus_enable +}; diff --git a/src/drivers/i2c/gpiomux/bus/chip.h b/src/drivers/i2c/gpiomux/bus/chip.h new file mode 100644 index 0000000..784a55b --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_BUS_CHIP_H__ +#define __I2C_GPIOMUX_BUS_CHIP_H__ + +struct drivers_i2c_gpiomux_bus_config { + char *name; +}; + +#endif /* __I2C_GPIOMUX_BUS_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b983bc8ce212ce05fe6b7f01a6d9092468e582 Gerrit-Change-Number: 46144 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... drivers/i2c: Add chip driver for GPIO based I2C multiplexer Add identifiers in ACPI tables for GPIO based I2C multiplexer. The multiplexer device defines the GPIO resource used to select the adapter/bus lines. The multiplexer adapter device defines the address to select the adapter/client lines. These ACPI identifiers are consumed by the i2c-mux-gpio kernel driver: https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Name (_HID, "PRP0001") // _HID: Hardware ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x02) { Package (0x02) { "compatible", "i2c-mux-gpio" }, Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45911 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/drivers/i2c/gpiomux/Kconfig A src/drivers/i2c/gpiomux/Makefile.inc A src/drivers/i2c/gpiomux/mux/Makefile.inc A src/drivers/i2c/gpiomux/mux/chip.h A src/drivers/i2c/gpiomux/mux/mux.c 5 files changed, 107 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/i2c/gpiomux/Kconfig b/src/drivers/i2c/gpiomux/Kconfig new file mode 100644 index 0000000..f09a641 --- /dev/null +++ b/src/drivers/i2c/gpiomux/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_GPIO_MUX + bool + default n + depends on HAVE_ACPI_TABLES + help + When enabled, add identifiers in ACPI tables for GPIO based I2C multiplexer. diff --git a/src/drivers/i2c/gpiomux/Makefile.inc b/src/drivers/i2c/gpiomux/Makefile.inc new file mode 100644 index 0000000..fec8d5b --- /dev/null +++ b/src/drivers/i2c/gpiomux/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux diff --git a/src/drivers/i2c/gpiomux/mux/Makefile.inc b/src/drivers/i2c/gpiomux/mux/Makefile.inc new file mode 100644 index 0000000..e51f706 --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux.c diff --git a/src/drivers/i2c/gpiomux/mux/chip.h b/src/drivers/i2c/gpiomux/mux/chip.h new file mode 100644 index 0000000..9906b25 --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/chip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_MUX_CHIP_H__ +#define __I2C_GPIOMUX_MUX_CHIP_H__ + +#include <acpi/acpi_device.h> +#include <types.h> + +#define MAX_NUM_MUX_GPIOS 4 + +struct drivers_i2c_gpiomux_mux_config { + /* GPIOs used to select the mux lines */ + uint32_t mux_gpio_count; + struct acpi_gpio mux_gpio[MAX_NUM_MUX_GPIOS]; +}; + +#endif /* __I2C_GPIOMUX_MUX_CHIP_H__ */ diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c new file mode 100644 index 0000000..66c8cc5 --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <stdlib.h> +#include <string.h> +#include "chip.h" + +static const char *i2c_gpiomux_mux_acpi_name(const struct device *dev) +{ + static char name[ACPI_NAME_BUFFER_SIZE]; + + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MUX%01.1X", dev->path.generic.id); + return name; +} + +static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + struct drivers_i2c_gpiomux_mux_config *config = config_of(dev); + struct acpi_dp *dsd = NULL; + const char *compat_string = "i2c-mux-gpio"; + struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS]; + int i; + + if (!dev->enabled || !scope || !path) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + for (i = 0; i < config->mux_gpio_count; i++) { + acpi_device_write_gpio(&config->mux_gpio[i]); + param[i].ref = path; + param[i].index = i; + param[i].pin = 0; + param[i].active_low = config->mux_gpio[i].active_low; + } + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "compatible", compat_string); + acpi_dp_add_gpio_array(dsd, "mux-gpios", param, config->mux_gpio_count); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_mux_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_mux_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_mux_fill_ssdt, +}; + +static void i2c_gpiomux_mux_enable(struct device *dev) +{ + if (!dev) + return; + + dev->ops = &i2c_gpiomux_mux_ops; +} + +struct chip_operations drivers_i2c_gpiomux_mux_ops = { + CHIP_NAME("I2C GPIO MUX Device") + .enable_dev = i2c_gpiomux_mux_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 19 Oct '20

19 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45700 ) Change subject: soc/amd/common/acpi: Convert to ASL 2.0 syntax ...................................................................... soc/amd/common/acpi: Convert to ASL 2.0 syntax Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/acpi/lpc.asl M src/soc/amd/common/acpi/thermal_zone.asl 3 files changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45700/1 diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f73340c..f638339 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -6,14 +6,14 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) + Return ((Arg0 * 4) + ACPIMMIO_GPIO0_BASE)) } /* Read pin control dword */ Method (GPRD, 0x1, Serialized) { /* Arg0 - GPIO pin control MMIO address */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (GPDW, SystemMemory, Local0, 4) Field (GPDW, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -26,12 +26,12 @@ { /* Arg0 - GPIO pin control MMIO address */ /* Arg1 - Value for control register */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (GPDW, SystemMemory, Local0, 4) Field (GPDW, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } Method (GPGB, 0x2) @@ -41,8 +41,8 @@ * Arg0 - GPIO pin control MMIO address * Arg1 - Desired byte (0 through 3) */ - Store (Multiply(Arg1, 8), Local2) - Return (And(ShiftRight(GPRD(Arg0), Local2), 0x000000FF)) + Local2 = Arg1 * 8 + Return ((GPRD (Arg0) >> Local2) & 0x000000FF) } Method (GPSB, 0x3) @@ -53,9 +53,9 @@ * Arg1 - Desired byte (0 through 3) * Arg2 - Value */ - Store (Multiply(Arg1, 8), Local2) - And(ShiftRight(GPRD(Arg0), Local2), 0xFFFFFF00, Local3) - ShiftLeft (Or(And(Arg2, 0x000000FF),Local3), Local2, Local4) + Local2 = Arg1 * 8 + Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 + Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 GPWR (Arg0, Local4) } diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index e4b0689..d2224e8 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -41,10 +41,10 @@ { CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address CreateDwordField(^CRS,^BAR1._BAS,ESPB) // Field to hold eSPI base address - And(BAR, 0xffffff00, Local0) - Store(Local0, SPIB) // SPI base address mapped - Add(Local0, 0x10000, Local1) - Store(Local1, ESPB) // eSPI base address mapped + Local0 = BAR & 0xffffff00 + SPIB = Local0 // SPI base address mapped + Local1 = Local0 + 0x10000 + ESPB = Local1 // eSPI base address mapped Return(CRS) } } diff --git a/src/soc/amd/common/acpi/thermal_zone.asl b/src/soc/amd/common/acpi/thermal_zone.asl index b33ba97..67dd7e7 100644 --- a/src/soc/amd/common/acpi/thermal_zone.asl +++ b/src/soc/amd/common/acpi/thermal_zone.asl @@ -48,16 +48,16 @@ Name (_STR, Unicode ("AMD CPU Core Thermal Sensor")) Method (_STA) { - If (LEqual (HTCE, One)) { + If (HTCE == One) { Return (0x0F) } Return (Zero) } Method (_TMP) { /* Current temp in tenths degree Kelvin. */ - Multiply (TNOW, 10, Local0) - ShiftRight (Local0, 3, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + Local0 = TNOW * 10 + Local0 >>= 3 + Return (Local0 + K10TEMP_KELVIN_OFFSET) } /* @@ -65,17 +65,17 @@ * P-State and power consumption in order to cool down. */ Method (_PSV) { /* Passive temp in tenths degree Kelvin. */ - Multiply (TLMT, 10, Local0) - ShiftRight (Local0, 1, Local0) - Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + Local0 = TLMT * 10 + Local0 >>= 1 + Local0 += K10TEMP_TLIMIT_OFFSET + Return (Local0 + K10TEMP_KELVIN_OFFSET) } Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ - Return (Add (_PSV, K10TEMP_HOT_OFFSET)) + Return (_PSV + K10TEMP_HOT_OFFSET) } Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ - Return (Add (_HOT, K10TEMP_HOT_OFFSET)) + Return (_HOT + K10TEMP_HOT_OFFSET) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd Gerrit-Change-Number: 45700 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: lib/imd: move struct definitions to a new header file
by Name of user not set (Code Review) 19 Oct '20

19 Oct '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46216 ) Change subject: lib/imd: move struct definitions to a new header file ...................................................................... lib/imd: move struct definitions to a new header file Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976 --- A src/include/imd_private.h M src/lib/imd.c 2 files changed, 40 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46216/1 diff --git a/src/include/imd_private.h b/src/include/imd_private.h new file mode 100644 index 0000000..43c3b7d --- /dev/null +++ b/src/include/imd_private.h @@ -0,0 +1,38 @@ +#ifndef _IMD_PRIVATE_H_ +#define _IMD_PRIVATE_H_ + +#include <commonlib/bsd/helpers.h> + +/* In-memory data structures. */ +struct imd_root_pointer { + uint32_t magic; + /* Relative to upper limit/offset. */ + int32_t root_offset; +} __packed; + +struct imd_entry { + uint32_t magic; + /* start is located relative to imd_root */ + int32_t start_offset; + uint32_t size; + uint32_t id; +} __packed; + +struct imd_root { + uint32_t max_entries; + uint32_t num_entries; + uint32_t flags; + uint32_t entry_align; + /* Used for fixing the size of an imd. Relative to the root. */ + int32_t max_offset; + struct imd_entry entries[0]; +} __packed; + +#define IMD_ROOT_PTR_MAGIC 0xc0389481 +#define IMD_ENTRY_MAGIC (~0xc0389481) +#define SMALL_REGION_ID CBMEM_ID_IMD_SMALL +#define LIMIT_ALIGN 4096 + +#define IMD_FLAG_LOCKED 1 + +#endif /* _IMD_PRIVATE_H */ diff --git a/src/lib/imd.c b/src/lib/imd.c index 0277965..ac19d76 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -7,40 +7,11 @@ #include <stdlib.h> #include <string.h> #include <types.h> +#include <imd_private.h> + /* For more details on implementation and usage please see the imd.h header. */ -static const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; -static const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; -static const uint32_t SMALL_REGION_ID = CBMEM_ID_IMD_SMALL; - -/* In-memory data structures. */ -struct imd_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __packed; - -struct imd_entry { - uint32_t magic; - /* start is located relative to imd_root */ - int32_t start_offset; - uint32_t size; - uint32_t id; -} __packed; - -struct imd_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - /* Used for fixing the size of an imd. Relative to the root. */ - int32_t max_offset; - struct imd_entry entries[0]; -} __packed; - -#define IMD_FLAG_LOCKED 1 - static void *relative_pointer(void *base, ssize_t offset) { intptr_t b = (intptr_t)base; -- To view, visit https://review.coreboot.org/c/coreboot/+/46216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976 Gerrit-Change-Number: 46216 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
by Patrick Georgi (Code Review) 19 Oct '20

19 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45899 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 The headers added are generated as per FSP v2376. Previous FSP version was 2295. Changes Include: - add GpioOverride UPD in Fspm.h - add new header FirmwareVersionInfo.h Cq-Depend: TBD Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h 2 files changed, 83 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h new file mode 100644 index 0000000..c375fee --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h @@ -0,0 +1,72 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include <IndustryStandard/SmBios.h> + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index 8155e85..fc167c5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -2708,7 +2708,17 @@ /** Offset 0x067E - Reserved **/ - UINT8 Reserved38[18]; + UINT8 Reserved38; + +/** Offset 0x067F - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable;1: Level 1 +**/ + UINT8 GpioOverride; + +/** Offset 0x0680 - Reserved +**/ + UINT8 Reserved39[16]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/45899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Gerrit-Change-Number: 45899 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: amd/picasso/verstage: replace rsa accel with modexp
by Kangheui Won (Code Review) 19 Oct '20

19 Oct '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45987 ) Change subject: amd/picasso/verstage: replace rsa accel with modexp ...................................................................... amd/picasso/verstage: replace rsa accel with modexp Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp. Instead of using hardware acceleration for whole RSA process, acclerating only calculation part(modexp) increases transparency without affecting boot time. BUG=b:169157796 BRANCH=zork TEST=build and flash, check time spent on RSA is not changed Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546 Signed-off-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/amd/picasso/psp_verstage/vboot_crypto.c 1 file changed, 32 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45987/1 diff --git a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c index 0bb9066..a5dbabc 100644 --- a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c @@ -8,6 +8,7 @@ #include "psp_verstage.h" #include <stddef.h> #include <string.h> +#include <swab.h> #include <vb2_api.h> static struct SHA_GENERIC_DATA_T sha_op; @@ -103,48 +104,53 @@ return VB2_SUCCESS; } -vb2_error_t vb2ex_hwcrypto_rsa_verify_digest(const struct vb2_public_key *key, - const uint8_t *sig, const uint8_t *digest) +vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key, + uint8_t *inout, + uint32_t *workbuf32, int exp) { - RSAPKCS_VERIFY_PARAMS RSAParams; + /* workbuf32 is guaranteed to be a length of + * 3 * key->arrsize * sizeof(uint32_t). + * Since PSP expects everything in LE and *inout is BE array, + * we'll use workbuf for temporary buffer for endian conversion. + */ + MOD_EXP_PARAMS mod_exp_param; + unsigned int key_bytes = key->arrsize * sizeof(uint32_t); + uint32_t *sig_swapped = workbuf32; + uint32_t *output_buffer = &workbuf32[key->arrsize]; + uint32_t *inout_32 = (uint32_t *)inout; uint32_t retval; - uint32_t exp = 65537; - uint32_t sig_size; - size_t digest_size; + int i; - /* PSP only supports 2K and 4K RSA */ + /* PSP only supports 2K and 4K modulus */ if (key->sig_alg != VB2_SIG_RSA2048 && key->sig_alg != VB2_SIG_RSA2048_EXP3 && key->sig_alg != VB2_SIG_RSA4096) { return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } - /* PSP only supports SHA256, SHA384 and SHA512*/ - if (key->hash_alg != VB2_HASH_SHA256 && - key->hash_alg != VB2_HASH_SHA384 && - key->hash_alg != VB2_HASH_SHA512) { - return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; + for(i = 0; i < key->arrsize; i++) { + sig_swapped[i] = swab32(inout_32[key->arrsize - i - 1]); } - if (key->sig_alg == VB2_SIG_RSA2048_EXP3) - exp = 3; - sig_size = vb2_rsa_sig_size(key->sig_alg); - digest_size = vb2_digest_size(key->hash_alg); + mod_exp_param.pExponent = (char *)&exp; + mod_exp_param.ExpSize = sizeof(exp); + mod_exp_param.pModulus = (char *)key->n; + mod_exp_param.ModulusSize = key_bytes; + mod_exp_param.pMessage = (char *)sig_swapped; + mod_exp_param.pOutput = (char *)output_buffer; - RSAParams.pHash = (char *)digest; - RSAParams.HashLen = digest_size; - RSAParams.pModulus = (char *)key->n; - RSAParams.ModulusSize = sig_size; - RSAParams.pExponent = (char *)&exp; - RSAParams.ExpSize = sizeof(exp); - RSAParams.pSig = (char *)sig; - - retval = svc_rsa_pkcs_verify(&RSAParams); + retval = svc_modexp(&mod_exp_param); if (retval) { printk(BIOS_ERR, "ERROR: HW crypto failed - errorcode: %#x\n", retval); - return VB2_ERROR_RSA_VERIFY_DIGEST; + return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; + } + + /* vboot expects results in *inout with BE, so copy & convert. */ + for(i = 0; i < key->arrsize; i++) { + inout_32[i] = swab32(output_buffer[key->arrsize - i - 1]); } return VB2_SUCCESS; + } -- To view, visit https://review.coreboot.org/c/coreboot/+/45987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546 Gerrit-Change-Number: 45987 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: mb/google/volteer: Enable USB4 retimer driver
by Duncan Laurie (Code Review) 19 Oct '20

19 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44919 ) Change subject: mb/google/volteer: Enable USB4 retimer driver ...................................................................... mb/google/volteer: Enable USB4 retimer driver Enable the USB4 retimer driver with GPP_H10 as the power control. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44919/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 4867fea..44f6738 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2717acd..82e3e5a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -392,6 +392,10 @@ device ref tbt_dma0 on probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H10)" + device generic 0 on end + end end device ref gna on end device ref north_xhci on end -- To view, visit https://review.coreboot.org/c/coreboot/+/44919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Gerrit-Change-Number: 44919 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: drivers/intel/usb4: Add driver for USB4 retimer device
by Duncan Laurie (Code Review) 19 Oct '20

19 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44918 ) Change subject: drivers/intel/usb4: Add driver for USB4 retimer device ...................................................................... drivers/intel/usb4: Add driver for USB4 retimer device The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn on the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 --- A src/drivers/intel/usb4/retimer/Kconfig A src/drivers/intel/usb4/retimer/Makefile.inc A src/drivers/intel/usb4/retimer/chip.h A src/drivers/intel/usb4/retimer/retimer.c 4 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44918/1 diff --git a/src/drivers/intel/usb4/retimer/Kconfig b/src/drivers/intel/usb4/retimer/Kconfig new file mode 100644 index 0000000..b2bd99c --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_INTEL_USB4_RETIMER + bool diff --git a/src/drivers/intel/usb4/retimer/Makefile.inc b/src/drivers/intel/usb4/retimer/Makefile.inc new file mode 100644 index 0000000..bca23aa --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_RETIMER) += retimer.c diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h new file mode 100644 index 0000000..789d824 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_RETIMER_H__ +#define __DRIVERS_INTEL_USB4_RETIMER_H__ + +#include <acpi/acpi_device.h> + +struct drivers_intel_usb4_retimer_config { + /* GPIO used to control power of retimer device. */ + struct acpi_gpio power_gpio; +}; + +#endif /* __DRIVERS_INTEL_USB4_RETIMER_H__ */ diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c new file mode 100644 index 0000000..3613012 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_simple.h> +#include <device/path.h> +#include <gpio.h> +#include <string.h> +#include "chip.h" + +/* Unique ID for the retimer _DSM. */ +#define INTEL_USB4_RETIMER_DSM_UUID "61788900-C470-42BB-80F0-23A313864593" + +/* + * Arg0: UUID + * Arg1: Revision ID (set to 1) + * Arg2: Function Index + * 0: Query command implemented + * 1: Query force power enable state + * 2: Set force power state + * Arg3: A package containing parameters for the function specified + * by the UUID, revision ID and function index. + */ + +static void usb4_retimer_cb_standard_query(void *arg) +{ + /* + * ToInteger (Arg1, Local2) + * If (Local2 == 1) { + * Return(Buffer() {0x07}) + * } + * Return (Buffer() {0x01}) + */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0x07); + acpigen_pop_len(); /* If */ + acpigen_write_return_singleton_buffer(0x01); +} + +static void usb4_retimer_cb_get_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Read power gpio into Local0 + * Store (\_SB.PCI0.GTXS (power_gpio), Local0) + * Return (Local0) + */ + acpigen_get_tx_gpio(power_gpio); + acpigen_write_return_op(LOCAL0_OP); +} + +static void usb4_retimer_cb_set_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Read power gpio into Local0 + * Store (\_SB.PCI0.GTXS (power_gpio), Local0) + */ + acpigen_get_tx_gpio(power_gpio); + + /* + * // Get argument for on/off from Arg3[0] + * Local2 = DeRefOf (Arg3[0]) + */ + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL2_OP); + + /* + * If (Local0 == Local2) { + * // Skip if already set + * Return (Zero) + * } + */ + acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL2_OP); + acpigen_write_return_integer(0); + acpigen_pop_len(); + + /* + * If (Local0 == 0) { + * // Turn power off + * \_SB.PCI0.CTXS (power_gpio) + * } + */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + acpigen_disable_tx_gpio(power_gpio); + acpigen_pop_len(); + + /* + * If (Local0 == 1) { + * // Turn power on + * \_SB.PCI0.STXS (power_gpio) + * } + */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_enable_tx_gpio(power_gpio); + acpigen_pop_len(); + + /* Return (Zero) */ + acpigen_write_return_integer(0); +} + +static void (*usb4_retimer_callbacks[3])(void *) = { + usb4_retimer_cb_standard_query, /* Function 0 */ + usb4_retimer_cb_get_power_state, /* Function 1 */ + usb4_retimer_cb_set_power_state, /* Function 2 */ +}; + +static void usb4_retimer_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_usb4_retimer_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + + if (!dev->enabled || !scope) + return; + if (!config->power_gpio.pin_count) { + printk(BIOS_ERR, "%s: Power GPIO required for %s\n", __func__, dev_path(dev)); + return; + } + + /* Write the _DSM that toggles power with provided GPIO. */ + acpigen_write_scope(scope); + acpigen_write_dsm(INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, + ARRAY_SIZE(usb4_retimer_callbacks), &config->power_gpio); + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static struct device_operations usb4_retimer_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_retimer_fill_ssdt, +}; + +static void usb4_retimer_enable(struct device *dev) +{ + dev->ops = &usb4_retimer_dev_ops; +} + +struct chip_operations drivers_intel_usb4_retimer_ops = { + CHIP_NAME("Intel USB4 Retimer") + .enable_dev = usb4_retimer_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Gerrit-Change-Number: 44918 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020