coreboot-gerrit October 2020

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Change in coreboot[master]: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume
by Felix Held (Code Review) 19 Oct '20

19 Oct '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44398 ) Change subject: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Gerrit-Change-Number: 44398 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Oct 2020 15:06:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume
by Marshall Dawson (Code Review) 19 Oct '20

19 Oct '20

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44398 ) Change subject: soc/amd/picasso: Skip SmmInfo to PSP on S3 resume ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Gerrit-Change-Number: 44398 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Oct 2020 15:04:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Fix typo in SMU argument base
by Marshall Dawson (Code Review) 19 Oct '20

19 Oct '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46505 ) Change subject: soc/amd/picasso: Fix typo in SMU argument base ...................................................................... soc/amd/picasso: Fix typo in SMU argument base Correct the base address. This should have no noticeable effect, as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The argument writes were not getting to any target. BUG=b:171037051 TEST=Run SST on morphius Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949 --- M src/soc/amd/picasso/include/soc/smu.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46505/1 diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index 128f4c4..eb7573c 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -11,7 +11,7 @@ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 -#define REG_ADDR_MESG_ARGS_BASE 0x0b10998 +#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 /* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949 Gerrit-Change-Number: 46505 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Enable CPU read for ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Hello build bot (Jenkins), Maulik V Vaghela, Stefan Reinauer, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#6). Change subject: util/ifdtool: Enable CPU read for ME region ...................................................................... util/ifdtool: Enable CPU read for ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch will enable read access to CSME region when locking. Also, we have enabled this change starting SKL/KBL. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Nico Huber (Code Review) 19 Oct '20

19 Oct '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... mb/siemens/chili: Add Chili variant This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Fac… Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/chili/Kconfig.name M src/mainboard/siemens/chili/mainboard.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/chili/Makefile.inc A src/mainboard/siemens/chili/variants/chili/board_info.txt A src/mainboard/siemens/chili/variants/chili/data.vbt A src/mainboard/siemens/chili/variants/chili/devicetree.cb A src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads A src/mainboard/siemens/chili/variants/chili/gpio.c A src/mainboard/siemens/chili/variants/chili/hda_verb.c A src/mainboard/siemens/chili/variants/chili/romstage.c 13 files changed, 481 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Thomas Heijligen: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index 8c919b5..fda571d 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -1,24 +1,29 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_SIEMENS_CHILI_BASE +if BOARD_SIEMENS_CHILI_BASE || BOARD_SIEMENS_CHILI_CHILI config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_CHILI_CHILI select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_SIEMENS_CHILI_CHILI select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION + select SMBIOS_PROVIDED_BY_MOBO if BOARD_SIEMENS_CHILI_CHILI select SOC_INTEL_CANNONLAKE_PCH_H select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_SIEMENS_CHILI_CHILI + select SECUNET_DMI if BOARD_SIEMENS_CHILI_CHILI config MAINBOARD_DIR string @@ -30,11 +35,13 @@ config MAINBOARD_PART_NUMBER string - default "Chili base board" + default "Chili base board" if BOARD_SIEMENS_CHILI_BASE + default "Chili" if BOARD_SIEMENS_CHILI_CHILI config VARIANT_DIR string default "base" if BOARD_SIEMENS_CHILI_BASE + default "chili" if BOARD_SIEMENS_CHILI_CHILI config DEVICETREE string @@ -56,4 +63,12 @@ bool default n +config SIEMENS_CHILI_DEBUG_USB + bool "Enable debug USB port" + depends on BOARD_SIEMENS_CHILI_CHILI + +config DRIVERS_INTEL_WIFI + bool + default n if BOARD_SIEMENS_CHILI_CHILI + endif diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name index a96a28c..ac4e31e 100644 --- a/src/mainboard/siemens/chili/Kconfig.name +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -4,3 +4,6 @@ config BOARD_SIEMENS_CHILI_BASE bool "-> Base board" + +config BOARD_SIEMENS_CHILI_CHILI + bool "-> Chili (AiO)" diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c index 42e132d..91395ea 100644 --- a/src/mainboard/siemens/chili/mainboard.c +++ b/src/mainboard/siemens/chili/mainboard.c @@ -6,7 +6,8 @@ static void mainboard_dev_init(struct device *dev) { - const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE); + const bool enable_usb = + CONFIG(BOARD_SIEMENS_CHILI_BASE) || CONFIG(SIEMENS_CHILI_DEBUG_USB); ec_enable_devices(enable_usb); } diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index 9c941c2..c1ec7e4 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -38,5 +38,11 @@ memupd->FspmTestConfig.VtdDisable = !vtd; get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + variant_romstage_params(memupd); + mainboard_init(); } + +__weak void variant_romstage_params(FSPM_UPD *const mupd) +{ +} diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/variant.h index 423608f..2bbe7d7 100644 --- a/src/mainboard/siemens/chili/variant.h +++ b/src/mainboard/siemens/chili/variant.h @@ -3,6 +3,10 @@ #ifndef _VARIANT_H_ #define _VARIANT_H_ +#include <fsp/soc_binding.h> + +void variant_romstage_params(FSPM_UPD *); + const struct pad_config *variant_gpio_table(size_t *num); #endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/variants/chili/Makefile.inc b/src/mainboard/siemens/chili/variants/chili/Makefile.inc new file mode 100644 index 0000000..251a291 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += hda_verb.c diff --git a/src/mainboard/siemens/chili/variants/chili/board_info.txt b/src/mainboard/siemens/chili/variants/chili/board_info.txt new file mode 100644 index 0000000..f5d6b2f --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/board_info.txt @@ -0,0 +1,2 @@ +Board name: Chili +Category: misc diff --git a/src/mainboard/siemens/chili/variants/chili/data.vbt b/src/mainboard/siemens/chili/variants/chili/data.vbt new file mode 100644 index 0000000..7c5b273 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/data.vbt Binary files differ diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb new file mode 100644 index 0000000..5a2fc01 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + register "speed_shift_enable" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # PCIe x16 + device pci 01.1 off end # PCIe x8 + device pci 01.2 off end # PCIe x4 + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # Imaging Processing Unit + device pci 08.0 off end # Gaussian mixture model, Neural network accelerator + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi Wifi + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/secunet/dmi + device i2c 0x57 on end # Serial EEPROM + end + chip drivers/i2c/lm96000 + device i2c 0x2e on end + register "vin[0].low" = " 1900 * 95/100" + register "vin[0].high" = " 1900 * 105/100" + register "vin[1].low" = " 1200 * 95/100" + register "vin[1].high" = " 1200 * 105/100" + register "vin[2].low" = " 3300 * 95/100" + register "vin[2].high" = " 3300 * 105/100" + register "vin[3].low" = " 5000 * 95/100" + register "vin[3].high" = " 5000 * 105/100" + register "vin[4].low" = "12000 * 95/100" + register "vin[4].high" = "12000 * 105/100" + + register "temp_in[0].low" = "-25" + register "temp_in[0].high" = " 85" + register "temp_in[1].low" = "-25" + register "temp_in[1].high" = " 85" + register "temp_in[2].low" = "-25" + register "temp_in[2].high" = " 85" + + register "fan[0]" = "{ + .mode = LM96000_FAN_HOTTEST_123, + .spinup = LM96000_SPINUP_2000MS, + .freq = LM96000_PWM_27_7KHZ, + .min_duty = 23, + }" + register "fan[1]" = "{ + .mode = LM96000_FAN_HOTTEST_123, + .spinup = LM96000_SPINUP_2000MS, + .freq = LM96000_PWM_27_7KHZ, + .min_duty = 23, + }" + + register "zone[0]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + register "zone[1]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + register "zone[2]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off # PCI Express Port 1 + device pci 00.0 on end # Debug (x1) + register "PcieRpEnable[0]" = "0" + register "PcieClkSrcUsage[2]" = "0" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # CORE (x1) + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # i210 (x1) + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[5]" = "0" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on end # VL805 Front Rack/UIB (x1) + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[1]" = "6" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "0" + end + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # VL805 Back MB (x1) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[0]" = "7" + register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[7]" = "0" + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on # PCI Express Port 17 + device pci 00.0 on end # NVMe (x4) + register "PcieRpEnable[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieRpSlotImplemented[16]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TraceHub + end +end diff --git a/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads new file mode 100644 index 0000000..fdb364c --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP2, + DP3, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c new file mode 100644 index 0000000..4b18e79 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE), +/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 UART0A_RXD 0x0000005044000702 */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* GPP_C9 UART0A_TXD 0x0000005144000700 */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GPP_C10 UART0A_RTS# 0x0000005244000700 */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* GPP_C11 UART0A_CTS# 0x0000005344000702 */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA 0x0000005844000402 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO 0x0000007544000300 */ PAD_NC(GPP_D21, NONE), +/* GPP_D22 GPIO 0x0000007644000300 */ PAD_NC(GPP_D22, NONE), +/* GPP_G1 GPIO 0x0000006d44000300 */ PAD_NC(GPP_G1, NONE), +/* GPP_G2 GPIO 0x0000006e44000300 */ PAD_NC(GPP_G2, NONE), +/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* I2S1_SFRM GPIO 0x0000000040000300 */ PAD_NC(I2S1_SFRM, NONE), +/* I2S1_TXD GPIO 0x0000000040000300 */ PAD_NC(I2S1_TXD, NONE), +/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ +/* GPD9 GPIO 0x0000006904000200 */ PAD_CFG_GPO(GPD9, 0, PWROK), +/* GPD11 GPIO 0x0000006b04000200 */ PAD_CFG_GPO(GPD11, 0, PWROK), +/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO 0x0000001c44000300 */ PAD_NC(GPP_K4, NONE), +/* GPP_K5 GPIO 0x0000001d44000300 */ PAD_NC(GPP_K5, NONE), +/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO 0x0000004844000300 */ PAD_NC(GPP_H0, NONE), +/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO 0x0000005244000300 */ PAD_NC(GPP_H10, NONE), +/* GPP_H15 GPIO 0x0000005744000300 */ PAD_NC(GPP_H15, NONE), +/* GPP_H17 GPIO 0x0000005944000300 */ PAD_NC(GPP_H17, NONE), +/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO 0x0000002484000200 */ PAD_CFG_GPO(GPP_E12, 0, PLTRST), +/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO 0x0000003544000300 */ PAD_NC(GPP_F5, NONE), +/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO 0x0000003844000300 */ PAD_NC(GPP_F8, NONE), +/* GPP_F9 GPIO 0x0000003944000300 */ PAD_NC(GPP_F9, NONE), +/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 GPIO 0x0000004644000300 */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 GPIO 0x0000004744000300 */ PAD_NC(GPP_F23, NONE), +/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 GPIO 0x0000003344000300 */ PAD_NC(GPP_J5, NONE), +/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/siemens/chili/variants/chili/hda_verb.c b/src/mainboard/siemens/chili/variants/chili/hda_verb.c new file mode 100644 index 0000000..f0e403a --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/hda_verb.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0xffffffff, /* Subsystem ID */ + 12, /* Number of entries below */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x110a4097), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, /* 0x14 Speaker OUT */ + (AZALIA_PINCFG_PORT_FIXED << 30) | + (AZALIA_PINCFG_LOCATION_INTERNAL << 24) | + (AZALIA_PINCFG_DEVICE_SPEAKER << 20) | + (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16) | + (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | + (1 << 4) | 0 + ), + AZALIA_PIN_CFG(0, 0x21, /* 0x21 Headphone OUT */ + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_FRONT << 24) | + (AZALIA_PINCFG_DEVICE_HP_OUT << 20) | + (AZALIA_PINCFG_CONN_COMBINATION << 16) | + (AZALIA_PINCFG_COLOR_BLACK << 12) | + (2 << 4) | 0 + ), + AZALIA_PIN_CFG(0, 0x19, /* 0x19 MIC2 */ + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_FRONT << 24) | + (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) | + (AZALIA_PINCFG_CONN_COMBINATION << 16) | + (AZALIA_PINCFG_COLOR_BLACK << 12) | + (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | + (3 << 4) | 0 + ), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* 0x12 Digital MIC */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(1)), /* 0x17 Mono OUT */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(2)), /* 0x18 MIC1 */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(3)), /* 0x1a LINE1 */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(4)), /* 0x1b LINE2 */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(5)), /* 0x1d PCBEEP */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(6)), /* 0x1e S/PDIF OUT */ + + /* HDMI/DP audio codec */ + 0x8086280b, /* Codec Vendor / Device ID: Intel Kabylake HDMI */ + 0xffffffff, /* Subsystem ID */ + 5, /* Number of entries below */ + + /* Enable 2nd & 3rd pin widgets first */ + 0x20878101, + 0x20878101, + 0x20878101, + 0x20878101, + AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_CFG_NC(1)), + AZALIA_PIN_CFG(2, 0x07, + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_REAR_PANEL << 24) | + (AZALIA_PINCFG_DEVICE_DIGITAL_OUT << 20) | + (AZALIA_PINCFG_CONN_OTHER_DIGITAL << 16) | + (1 << 4) | 0 + ), + /* Disable 2nd & 3rd pin widgets again */ + 0x20878100, + 0x20878100, + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c new file mode 100644 index 0000000..ebffc8d3 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <console/console.h> +#include <fsp/soc_binding.h> + +#include "../../variant.h" + +void variant_romstage_params(FSPM_UPD *const mupd) +{ + uint8_t eth_enable = 1; + + get_option(&eth_enable, "ethernet1"); + if (!eth_enable) { + printk(BIOS_DEBUG, "Disabling ethernet1.\n"); + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 5); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 28 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by build bot (Jenkins) (Code Review) 19 Oct '20

19 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 27: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/romstage.c: https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… PS27, Line 46: __weak void variant_romstage_params(FSPM_UPD *const mupd) need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/gpio.c: https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… PS27, Line 44: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… PS27, Line 49: /* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/27/src/mainboard/siemens/chi… PS27, Line 95: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 27 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 13:00:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superio/nuvoton: Correct NCT6791D COM A mux toggle
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46521 ) Change subject: superio/nuvoton: Correct NCT6791D COM A mux toggle ...................................................................... superio/nuvoton: Correct NCT6791D COM A mux toggle Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like on the other two Nuvoton Super I/Os, so fold the conditionals together. Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/superio/nuvoton/common/early_serial.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46521/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index ed5fdba..3986789 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -53,14 +53,11 @@ nuvoton_pnp_enter_conf_state(dev); if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || + CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A) || CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0); - if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A)) - /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x00); - pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); -- To view, visit https://review.coreboot.org/c/coreboot/+/46521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Gerrit-Change-Number: 46521 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Angel Pons (Code Review) 19 Oct '20

19 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 26: Code-Review+2 Would +3 if I had this board :) -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 26 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 12:06:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Enable CPU read for ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Hello build bot (Jenkins), Maulik V Vaghela, Stefan Reinauer, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#5). Change subject: util/ifdtool: Enable CPU read for ME region ...................................................................... util/ifdtool: Enable CPU read for ME region Using ifdtool after generating and flashing coreboot image for locking RW access for JSL platform, 1. Flashrom should return success while erasing the SI_ME region and 2. After rebooting the DUT should boot into OS without any issues. But we see DUT is rebooting continuously after flashing the newly generated coreboot.bin.new This patch adds the code to enable CPU read for ME region after the ME lock operation. The security impact is taken care as the private data stored by CSE is all encrypted. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 19 Oct '20

19 Oct '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... Patch Set 4: (5 comments) https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@8 PS3, Line 8: > Please desribe the problem first. […] Done https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@9 PS3, Line 9: This patch adds the code to enable CPU read > … for ME region Done https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@13 PS3, Line 13: return > returns Done https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@14 PS3, Line 14: boot > boots Done https://review.coreboot.org/c/coreboot/+/46441/3//COMMIT_MSG@15 PS3, Line 15: Drawlat EVT . > Please remove the space before the dot/period. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Oct 2020 12:03:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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