coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/xeon_sp/skx/: Clean up soc_util.c
by Marc Jones (Code Review) 23 Oct '20

23 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46094 ) Change subject: soc/intel/xeon_sp/skx/: Clean up soc_util.c ...................................................................... soc/intel/xeon_sp/skx/: Clean up soc_util.c Remove unused c_util.c helper functions and clean up soc_util.h in preparation for merging common code with cpx/. Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 2 files changed, 13 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46094/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 0eac836..5e6f5ef 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -5,34 +5,27 @@ #include <hob_iiouds.h> #include <hob_memmap.h> -#include <acpi/acpi.h> -#include <soc/util.h> struct iiostack_resource { uint8_t no_of_stacks; STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -uintptr_t get_tolm(uint32_t bus); -void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); -uintptr_t get_cha_mmcfg_base(uint32_t bus); -uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory - -uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); - -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); void get_iiostack_info(struct iiostack_resource *info); -int get_threads_per_package(void); -int get_platform_thread_count(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); - -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, - uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); - -const struct SystemMemoryMapHob *get_system_memory_map(void); void xeonsp_init_cpu_config(void); -void set_bios_init_completion(void); + void config_reset_cpl3_csrs(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread); + +int get_platform_thread_count(void); +int get_threads_per_package(void); +const struct SystemMemoryMapHob *get_system_memory_map(void); + +void set_bios_init_completion(void); + #endif /* _SOC_UTIL_H_ */ + diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 179b08f..e6083c5 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -17,61 +17,6 @@ #include <soc/util.h> #include <timer.h> -/* - * Get TOLM CSR B0:D5:F0:Offset_d0h - */ -uintptr_t get_tolm(uint32_t bus) -{ - uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TOLM_CSR); - uintptr_t addr = w & 0xfc000000; - printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr); - return addr; -} - -void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit) -{ - uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TSEG_BASE_CSR); - uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TSEG_LIMIT_CSR); - *base = w1 & 0xfff00000; - *limit = wh & 0xfff00000; -} - -/* - * Get MMCFG CSR B1:D29:F1:Offset_C0h - */ -uintptr_t get_cha_mmcfg_base(uint32_t bus) -{ - uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, - CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR); - uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, - CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4); - uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26); - printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n", - wl, wh, addr); - return addr; -} - -uint32_t top_of_32bit_ram(void) -{ - uintptr_t mmcfg, tolm; - uint32_t bus0 = 0, bus1 = 0; - uint32_t base = 0, limit = 0; - - get_cpubusnos(&bus0, &bus1, NULL, NULL); - - mmcfg = get_cha_mmcfg_base(bus1); - tolm = get_tolm(bus0); - printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n", - bus0, bus1, mmcfg, tolm); - get_tseg_base_lim(bus0, &base, &limit); - printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit); - - /* We will use TSEG base as the top of DRAM */ - return base; -} /* * +-------------------------+ TOLM @@ -101,12 +46,7 @@ * +-------------------------+ */ -uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) -{ - return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset); -} - -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { size_t hob_size; const IIO_UDS *hob; -- To view, visit https://review.coreboot.org/c/coreboot/+/46094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Gerrit-Change-Number: 46094 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Felix Singer (Code Review) 23 Oct '20

23 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 00:31:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Felix Singer (Code Review) 23 Oct '20

23 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 11: Code-Review+1 > Well, I'm not sure if it's really worth adding a function for two checks, where one will vanish soon (when SKL uses common acpi code). I could add it, though How is this done in common ACPI code? -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 00:29:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Felix Singer (Code Review) 23 Oct '20

23 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 00:19:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM conf...
by Furquan Shaikh (Code Review) 23 Oct '20

23 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46652 ) Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… File src/mainboard/google/dedede/dsdt.asl: https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… PS2, Line 42: <soc/intel/common/acpi/lpit.asl> > Regarding notifications, looking at the LPIT table […] Ack. Thanks Evan and Karthik. -- To view, visit https://review.coreboot.org/c/coreboot/+/46652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Gerrit-Change-Number: 46652 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 23:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 14: > Patch Set 13: Code-Review+2 > > I'll pretend I didn't see the unrelated cosmetic changes. They were not intended. Dropped -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 23:12:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Frans Hendriks, Jeremy Soller, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Tim Wawrzynczak, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46462 to look at the new patch set (#14). Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 51 files changed, 2 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46462/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 11: > Patch Set 11: Code-Review+2 > > Generally, a tiny function (e.g. cpu_isst_capable()) would be > useful. Then we wouldn't have to repeat the expression and > wouldn't need the bit definition anywhere else. Well, I'm not sure if it's really worth adding a function for two checks, where one will vanish soon (when SKL uses common acpi code). I could add it, though -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 23:08:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add empty _DSM for TCSS DMA devices
by Duncan Laurie (Code Review) 23 Oct '20

23 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46641 ) Change subject: soc/intel/tigerlake: Add empty _DSM for TCSS DMA devices ...................................................................... soc/intel/tigerlake: Add empty _DSM for TCSS DMA devices This empty _DSM is required for the SOC to properly enter S0ix. The same empty _DSM exists for the TCSS XHCI and PCIe root port devices in the DSDT so just I just declared it here for consistency rather than putting it in the SSDT. BUG=b:171310928 TEST=authorize PCI tunnel on TBT dock and ensure that the system can still enter S0ix and the residency counter increases. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I016b07c5b497b06ded1e2c81ec149e3d0fc161bb --- M src/soc/intel/tigerlake/acpi/tcss_dma.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46641/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 085990d..e8e2d0e 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -92,3 +92,8 @@ { Return (Package() { 0x6D, 4 }) } + +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0 }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I016b07c5b497b06ded1e2c81ec149e3d0fc161bb Gerrit-Change-Number: 46641 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM conf...
by Karthik Ramasubramanian (Code Review) 23 Oct '20

23 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46652 ) Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… File src/mainboard/google/dedede/dsdt.asl: https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… PS2, Line 42: <soc/intel/common/acpi/lpit.asl> > From what I can tell no. We already don't expose an LPIT table, so that's moot. […] Regarding notifications, looking at the LPIT table Display On/Off Notifications are no-op. S0IX Entry/Exit Notifications notify: 1) EC - Only Wilco EC has registered for S0IX notifications. I don't see ChromeEC registering an hooks. 2) Mainboard - Mainboard hooks are removed in this CL. 3) GPIO PM - GPIO PM hooks are registered only for cannonlake and alderlake. -- To view, visit https://review.coreboot.org/c/coreboot/+/46652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Gerrit-Change-Number: 46652 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2020