coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/46461/10/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/46461/10/src/soc/intel/skylake/acp… PS10, Line 38: CPUID_1_ECX > That would be EIST. We'd want to check CPUID_6_EAX[7]. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 21:48:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 22 Oct '20

22 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46461 to look at the new patch set (#11). Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... soc/intel/skl: replace conditional on dt option reading CPUID for CPPC Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46461/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM conf...
by Evan Green (Code Review) 22 Oct '20

22 Oct '20

Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46652 ) Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… File src/mainboard/google/dedede/dsdt.asl: https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded… PS2, Line 42: <soc/intel/common/acpi/lpit.asl> > Do we lose any functionality in the kernel by not exposing LPIT? We won't really use any function no […] From what I can tell no. We already don't expose an LPIT table, so that's moot. This PNP0D80 device is all that's left. Assuming nothing in firmware land is relying on those ACPI S0 notification methods being called, the only part the kernel would look at is the device constraints in [1]. From what I can see in lpit.asl that's only initialized to a sentinal node now with no real device constraints. So the kernel should be ok. [1] https://source.corp.google.com/chromeos_public/src/third_party/kernel/v5.4/… -- To view, visit https://review.coreboot.org/c/coreboot/+/46652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Gerrit-Change-Number: 46652 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 21:41:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Rename cpx_generate_p_state_entries()
by Marc Jones (Code Review) 22 Oct '20

22 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46598 ) Change subject: soc/intel/xeon_sp: Rename cpx_generate_p_state_entries() ...................................................................... soc/intel/xeon_sp: Rename cpx_generate_p_state_entries() Prepare for common ACPI. Rename cpx_generated_p_state_entries() to the common soc_power_states_generation() function. Add empty soc_power_states_generation() to skx. Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/soc_acpi.c 4 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46598/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 5a908da..3066dda2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -261,8 +261,9 @@ /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - /* Generate P-state tables */ - cpx_generate_p_state_entries(core_id, threads_per_package); + /* Soc specific power states generation */ + soc_power_states_generation(core_id, threads_per_package); + acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 19d196d..8820517 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -123,8 +123,8 @@ acpigen_pop_len(); } -/* To be renamed soc_power_states_generation() */ -void cpx_generate_p_state_entries(int core, int cores_per_package) +/* TODO: See if we can use the common generate_p_state_entries */ +void soc_power_states_generation(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 75859e83..61639d2 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -22,7 +22,6 @@ void motherboard_fill_fadt(acpi_fadt_t *fadt); -void cpx_generate_p_state_entries(int core, int cores_per_package); int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 7462d72..df2550c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -171,6 +171,10 @@ acpigen_pop_len(); } +void soc_power_states_generation(int core, int cores_per_package) +{ +} + unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) { struct device *cpu; -- To view, visit https://review.coreboot.org/c/coreboot/+/46598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875 Gerrit-Change-Number: 46598 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/skx: Move skx specific FADT setting
by Marc Jones (Code Review) 22 Oct '20

22 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46597 ) Change subject: soc/intel/xeon_sp/skx: Move skx specific FADT setting ...................................................................... soc/intel/xeon_sp/skx: Move skx specific FADT setting Prepare for common ACPI. Move the skx specific FADT settings from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt() to match common/block/acpi.c. Change-Id: I04873d13d822de514acbb58501171285bd5b020e Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 2 files changed, 64 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46597/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index f0b7df9..c14e7c8 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -137,82 +137,53 @@ fadt->sci_int = acpi_sci_irq(); - /* TODO: enabled SMM mode switch when SMM handlers are set up. */ - if (0 && permanent_smi_handler()) { + if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } - /* Power Control */ fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); - /* Control Registers - Length */ fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; - fadt->duty_width = 0; - /* RTC Registers */ - fadt->day_alrm = 0x0d; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; - /* PM1 Status & PM1 Enable */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - /* PM1 Control Registers */ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; + fadt->x_gpe0_blk.addrh = 0; } unsigned long southbridge_write_acpi_tables(const struct device *device, diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 56ed0ce..7462d72 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -55,6 +55,48 @@ return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SEALED_CASE); + fadt->flags |= ACPI_FADT_SLEEP_TYPE; + + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + +} + void uncore_inject_dsdt(const struct device *device) { size_t hob_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/46597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04873d13d822de514acbb58501171285bd5b020e Gerrit-Change-Number: 46597 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move uncore_inject_dsdt() call
by Marc Jones (Code Review) 22 Oct '20

22 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46596 ) Change subject: soc/intel/xeon_sp: Move uncore_inject_dsdt() call ...................................................................... soc/intel/xeon_sp: Move uncore_inject_dsdt() call Prepare for common ACPI code. Move uncore_inject_dsdt() to the uncore device acpi_inject_dsdt call. Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 6 files changed, 7 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46596/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 658c951..5a908da 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -214,9 +214,6 @@ acpigen_write_name_dword("NVSA", (uint32_t)gnvs); acpigen_pop_len(); } - - /* Add IIOStack ACPI Resource Templates */ - uncore_inject_dsdt(); } int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index cf84334..19d196d 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -57,11 +57,7 @@ ACPI_FADT_S4_RTC_WAKE); } -/* - * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() - * with a call from the common/function or find another way to call this at the correct place - */ -void uncore_inject_dsdt(void) +void uncore_inject_dsdt(const struct device *device) { struct iiostack_resource stack_info = {0}; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index b46914d..75859e83 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -24,7 +24,7 @@ void cpx_generate_p_state_entries(int core, int cores_per_package); int calculate_power(int tdp, int p1_ratio, int ratio); -void uncore_inject_dsdt(void); +void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index c446a51..f0b7df9 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -247,9 +247,6 @@ acpigen_write_name_dword("NVSA", (uint32_t)gnvs); acpigen_pop_len(); } - - // Add IIOStack ACPI Resource Templates - uncore_inject_dsdt(); } diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index afbcf84..56ed0ce 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -55,11 +55,7 @@ return pci_read_config32(dev, PMC_ACPI_CNT); } -/* - * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() - * with a call from the common/function or find another way to call this at the correct place - */ -void uncore_inject_dsdt(void) +void uncore_inject_dsdt(const struct device *device) { size_t hob_size; const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a549acb..332b9a4 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -5,6 +5,7 @@ #include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -274,6 +275,9 @@ .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_inject_dsdt = uncore_inject_dsdt, +#endif }; static const unsigned short mmapvtd_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94 Gerrit-Change-Number: 46596 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move ACPI prototypes from chip.h
by Marc Jones (Code Review) 22 Oct '20

22 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46595 ) Change subject: soc/intel/xeon_sp: Move ACPI prototypes from chip.h ...................................................................... soc/intel/xeon_sp: Move ACPI prototypes from chip.h Prepare for common ACPI. Move the soc ACPI function prototypes from cpx and skx chip.h to include/soc/acpi.h. Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/chip.h M src/soc/intel/xeon_sp/skx/soc_acpi.c 7 files changed, 5 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46595/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 8d3e86a..658c951 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -23,8 +23,6 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" - static int acpi_sci_irq(void) { int sci_irq = 9; diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e7c146c..434b343 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -99,10 +99,4 @@ typedef struct soc_intel_xeon_sp_cpx_config config_t; -/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ -void cpx_generate_p_state_entries(int core, int cores_per_package); -int calculate_power(int tdp, int p1_ratio, int ratio); -void uncore_inject_dsdt(void); -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); - #endif diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index fab2211..cf84334 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -17,8 +17,6 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" - /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 6a76ef2..b46914d 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -22,4 +22,9 @@ void motherboard_fill_fadt(acpi_fadt_t *fadt); +void cpx_generate_p_state_entries(int core, int cores_per_package); +int calculate_power(int tdp, int p1_ratio, int ratio); +void uncore_inject_dsdt(void); +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); + #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index cbafbdb..c446a51 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -15,8 +15,6 @@ #include <soc/pm.h> #include <string.h> -#include "chip.h" - acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = 0; diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index adb70e5..0860899 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -76,8 +76,4 @@ typedef struct soc_intel_xeon_sp_skx_config config_t; -/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ -void uncore_inject_dsdt(void); -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); - #endif diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b6b39f2..afbcf84 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -18,8 +18,6 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" - /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Gerrit-Change-Number: 46595 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/xeon_sp/skx: Update get_iiostack_info()
by Marc Jones (Code Review) 22 Oct '20

22 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46307 ) Change subject: src/soc/intel/xeon_sp/skx: Update get_iiostack_info() ...................................................................... src/soc/intel/xeon_sp/skx: Update get_iiostack_info() Add Pci64BitResourceAllocation return value to get_iiostack_info(). This matches cpx function and is used in future de-duplication. Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46307/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index d641f76..76f7c8b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -11,7 +11,7 @@ STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -void get_iiostack_info(struct iiostack_resource *info); +uint8_t get_iiostack_info(struct iiostack_resource *info); void xeonsp_init_cpu_config(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 8b29e7f..3b37ca3 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -288,7 +288,7 @@ return get_cpu_count() * get_threads_per_package(); } -void get_iiostack_info(struct iiostack_resource *info) +uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -310,6 +310,8 @@ memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } + + return hob->PlatformData.Pci64BitResourceAllocation; } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/46307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Gerrit-Change-Number: 46307 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Nico Huber (Code Review) 22 Oct '20

22 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/46461/10/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/46461/10/src/soc/intel/skylake/acp… PS10, Line 38: CPUID_1_ECX That would be EIST. We'd want to check CPUID_6_EAX[7]. -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 21:25:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Nico Huber (Code Review) 22 Oct '20

22 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 10: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 21:22:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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