coreboot-gerrit October 2020

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Change in coreboot[master]: [TEST] util/abuild: Redirect output back to /dev/null
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45605 ) Change subject: [TEST] util/abuild: Redirect output back to /dev/null ...................................................................... [TEST] util/abuild: Redirect output back to /dev/null Commit 0d431ac removed the redirection. Try adding it back again. Change-Id: I872118b7dd68d5cf3bdaba0413287f41844cef3c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45605/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 7561495..538b7d3 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -821,7 +821,7 @@ printf "%s" "$configoptions" > "$TMPCFG" $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" allnoconfig printf "%s" "$configoptions" >> "$TMPCFG" - yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig + yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig > /dev/null 2>&1 BUILDPREFIX= if [ "$scanbuild" = "true" ]; then scanbuild_out=$TARGET/sharedutils-scanbuild -- To view, visit https://review.coreboot.org/c/coreboot/+/45605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872118b7dd68d5cf3bdaba0413287f41844cef3c Gerrit-Change-Number: 45605 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m: Update macros
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45008 ) Change subject: util/intelp2m: Update macros ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Gerrit-Change-Number: 45008 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:33:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Fix typos
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45007 ) Change subject: util/intelp2m: Fix typos ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697 Gerrit-Change-Number: 45007 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:33:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Tim Wawrzynczak (Code Review) 23 Oct '20

23 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:29:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Nico Huber (Code Review) 23 Oct '20

23 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 13: Code-Review+2 I'll pretend I didn't see the unrelated cosmetic changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:19:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Nico Huber (Code Review) 23 Oct '20

23 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 11: Code-Review+2 Generally, a tiny function (e.g. cpu_isst_capable()) would be useful. Then we wouldn't have to repeat the expression and wouldn't need the bit definition anywhere else. -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Oct 2020 22:16:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Use `config_of` where possible
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45714 ) Change subject: sb/intel/lynxpoint: Use `config_of` where possible ...................................................................... sb/intel/lynxpoint: Use `config_of` where possible This eliminates the need to perform null-checking. Change-Id: I88f7867d2b446a20a80417cd3758bd5406165fca Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45714/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fad83b1..dc16c37 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -174,7 +174,7 @@ u32 reg32; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -636,7 +636,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3e1f63b..4dd383b 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -145,12 +145,8 @@ rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - if (dev->chip_info != NULL) { - struct southbridge_intel_lynxpoint_config *config; - - config = dev->chip_info; - rpc.coalesce = config->pcie_port_coalesce; - } + struct southbridge_intel_lynxpoint_config *config = config_of(dev); + rpc.coalesce = config->pcie_port_coalesce; } rp = root_port_number(dev); @@ -501,7 +497,7 @@ static void pch_pcie_early(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct southbridge_intel_lynxpoint_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); int is_lp = pch_is_lp(); @@ -559,7 +555,7 @@ } /* Allow ASPM to be forced on in devicetree */ - if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) + if ((config->pcie_port_force_aspm & (1 << (rp - 1)))) do_aspm = 1; printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/45714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f7867d2b446a20a80417cd3758bd5406165fca Gerrit-Change-Number: 45714 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Align with Elkhart Lake
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45779 ) Change subject: soc/intel/jasperlake: Align with Elkhart Lake ...................................................................... soc/intel/jasperlake: Align with Elkhart Lake Change-Id: I4ac041081a0c7b97ee7069b7893bd9c1f3d340d4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/meminit.h M src/soc/intel/jasperlake/me.c M src/soc/intel/jasperlake/p2sb.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/jasperlake/reset.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/jasperlake/systemagent.c 13 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45779/1 diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8673da1..08f44b4 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -3,16 +3,16 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> -#include <device/device.h> -#include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 3a50929..382bbf7 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -2,12 +2,12 @@ #include <arch/cpu.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> +#include <device/pci.h> #include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 235dc6e..c88efc8 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -2,11 +2,11 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067..ab3e42f 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <arch/ioapic.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> @@ -67,7 +67,7 @@ static void pch_enable_ioapic(const struct device *dev) { - u32 reg32; + uint32_t reg32; /* PCH-LP has 120 redirection entries */ const int redir_entries = 120; @@ -126,7 +126,7 @@ itss_irq_init(pch_interrupt_routing); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; + uint8_t int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..0916436 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> -#include <device/mmio.h> #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> +#include <device/mmio.h> #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> diff --git a/src/soc/intel/jasperlake/include/soc/meminit.h b/src/soc/intel/jasperlake/include/soc/meminit.h index 5ba3e69..f3555ac 100644 --- a/src/soc/intel/jasperlake/include/soc/meminit.h +++ b/src/soc/intel/jasperlake/include/soc/meminit.h @@ -3,8 +3,8 @@ #ifndef _SOC_JASPERLAKE_MEMINIT_H_ #define _SOC_JASPERLAKE_MEMINIT_H_ -#include <types.h> #include <fsp/soc_binding.h> +#include <types.h> /* Number of dq bits controlled per dqs */ #define DQ_BITS_PER_DQS 8 diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index b40b4dc..d00702e 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> -#include <intelblocks/cse.h> #include <console/console.h> +#include <intelblocks/cse.h> #include <soc/me.h> static void dump_me_status(void *unused) diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c index 169cde6..0ddd007 100644 --- a/src/soc/intel/jasperlake/p2sb.c +++ b/src/soc/intel/jasperlake/p2sb.c @@ -13,7 +13,7 @@ } /* Remove the host accessing right to PSF register range. - * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable sideband * access for PCI Root Bridge. */ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index ed6a31d..a3564b6 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -2,8 +2,8 @@ #include <bootstate.h> #include <console/console.h> -#include <device/mmio.h> #include <device/device.h> +#include <device/mmio.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index ebe46b1..69282ee 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -7,15 +7,16 @@ #define __SIMPLE_DEVICE__ -#include <device/mmio.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_def.h> -#include <console/console.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> +#include <security/vboot/vbnv.h> #include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -24,7 +25,6 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> -#include <security/vboot/vbnv.h> /* * SMI diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index 1f7ea3c..fe3d769 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -2,9 +2,9 @@ #include <cf9_reset.h> #include <console/console.h> +#include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> -#include <fsp/util.h> #include <soc/intel/common/reset.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index bbdcb68..11b631b 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -1,22 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> #include <smp/node.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <string.h> +#include <types.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 080446c..73f7963 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/device.h> #include <delay.h> +#include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <intelblocks/systemagent.h> #include <intelblocks/power_limit.h> +#include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ac041081a0c7b97ee7069b7893bd9c1f3d340d4 Gerrit-Change-Number: 45779 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#26). Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/block/acpi: add code for CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. This way all SoCs using the common code get the CPPC entries added. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 26 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46465 to look at the new patch set (#15). Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/acpigen.c M src/soc/intel/skylake/acpi.c 2 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46465/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020