coreboot-gerrit October 2020

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Change in coreboot[master]: soc/mediatek/mt8192: add dram log prefix
by Xi Chen (Code Review) 23 Oct '20

23 Oct '20

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46585 ) Change subject: soc/mediatek/mt8192: add dram log prefix ...................................................................... soc/mediatek/mt8192: add dram log prefix 1 Add dram log prefix: [MEM] 2 Print error code when memtest fails. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I6c53c9cecf5996227a3e343fc703b9880d9afeac --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/memory.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46585/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 1d1cf7b..2932f25 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -32,10 +32,14 @@ bool default n help - This options enables DRAM calibration with multiple frequencies (low, + This option enables DRAM calibration with multiple frequencies (low, medium and high) for DVFS feature. config MEMORY_TEST bool default y + help + This option will do memory basic compare test to verify the dram read + or write is as expect. + endif diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c old mode 100644 new mode 100755 index b5363b0..19a702d --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -15,13 +15,13 @@ const struct ddr_base_info *ddr_info = &dparam->ddr_info; for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { - int i = complex_mem_test(addr, 0x2000); + int result = complex_mem_test(addr, 0x2000); printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s\n", - (i == 0) ? "pass" : "fail"); + (result == CB_SUCCESS) ? "pass" : "fail"); - if (i != 0) { - printk(BIOS_ERR, "DRAM memory test failed\n"); + if (result != 0) { + printk(BIOS_ERR, "[MEM] DRAM memory test failed: %d\n", result); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c53c9cecf5996227a3e343fc703b9880d9afeac Gerrit-Change-Number: 46585 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: soc/mediatek/mt8192: disable_l2c_sram in ramstage
by Yidi Lin (Code Review) 23 Oct '20

23 Oct '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46387 to review the following change. Change subject: soc/mediatek/mt8192: disable_l2c_sram in ramstage ...................................................................... soc/mediatek/mt8192: disable_l2c_sram in ramstage Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/mmu_operations.c M src/soc/mediatek/mt8192/soc.c 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46387/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8bc7b74..891d38a 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c new file mode 100644 index 0000000..fb3620e --- /dev/null +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 9850fa6..6978406 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0 Gerrit-Change-Number: 46387 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 23 Oct '20

23 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Maulik V Vaghela, Rizwan Qureshi, Stefan Reinauer, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#10). Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... util/ifdtool: Enable CPU read of the ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch provides a command line option "-r" which will enable read access to CSME region when locking. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 10 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in em100[master]: em100: Always install signal handler
by Stefan Reinauer (Code Review) 23 Oct '20

23 Oct '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/45538 ) Change subject: em100: Always install signal handler ...................................................................... em100: Always install signal handler Always catch SIGINT, because we don't want the tool to be interrupted half way through operations. This might leave the EM100Pro in a bad state that requires physically reconnecting the device. This renders the tool virtually unusable for lab setups. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I649dc491f68f764fdb1352599ff17b36e3d39fd8 --- M em100.c 1 file changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/38/45538/1 diff --git a/em100.c b/em100.c index 49d0d1e..580290a 100644 --- a/em100.c +++ b/em100.c @@ -840,6 +840,7 @@ unsigned long address_offset = 0; unsigned int spi_start_address = 0; const char *voltage = NULL; + struct sigaction signal_action; while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", longopts, &idx)) != -1) { @@ -936,6 +937,18 @@ if (desiredchip && !chip) return 1; + /* Set up signal handler. This is used for two reasons: + * 1) to create a way to cleanly exit trace mode. + * 2) to make sure that the em100 is not left in an improper state + * when receiving SIGINT for other reasons during operation. In + * this second case, we just ignore SIGINT until em100 naturally + * terminates or receives a second signal. This is OK because the + * utility is short-running in nature. + */ + signal_action.sa_handler = exit_handler; + signal_action.sa_flags = 0; + sigemptyset(&signal_action.sa_mask); + sigaction(SIGINT, &signal_action, NULL); if (em100.hwversion == HWVERSION_EM100PRO || em100.hwversion == HWVERSION_EM100PRO_EARLY) { printf("MCU version: %d.%02d\n", em100.mcu >> 8, em100.mcu & 0xff); @@ -1177,8 +1190,6 @@ } if (trace || terminal) { - struct sigaction signal_action; - if ((holdpin == NULL) && (!set_hold_pin_state(&em100, 3))) { printf("Error: Failed to set EM100 to input\n"); return 1; @@ -1200,10 +1211,6 @@ } printf(". Press CTL-C to exit.\n\n"); - signal_action.sa_handler = exit_handler; - signal_action.sa_flags = 0; - sigemptyset(&signal_action.sa_mask); - sigaction(SIGINT, &signal_action, NULL); while (!do_exit_flag) { if (trace) -- To view, visit https://review.coreboot.org/c/em100/+/45538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I649dc491f68f764fdb1352599ff17b36e3d39fd8 Gerrit-Change-Number: 45538 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Usha P (Code Review) 23 Oct '20

23 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Maulik V Vaghela, Rizwan Qureshi, Stefan Reinauer, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46441 to look at the new patch set (#9). Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... util/ifdtool: Enable CPU read of the ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch provides a command line option "-r" which will enable read access to CSME region when locking. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46441/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 9 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code
by Hung-Te Lin (Code Review) 23 Oct '20

23 Oct '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41503 ) Change subject: mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code ...................................................................... mb/google/kukui: Change AP ADC channel 4 to be high bits of RAM code Kukui (eMCP, discrete) and Jacuzzi (discrete) are currently sharing same memory code table with only one ADC (12 levels) and we are running out of RAM IDs. Considering there may be lots of requests of adding new second source DRAM in future, we decided to increase the RAM code mapping table instead of doing model-specific table. Now both ADC 2 and 4 will be RAM code, and SKU straps will be moved from AP (ADC 2) to EC. All existing devices should have grounded both AP SKU and EC SKU (e.g., 0) so there should be no backward compatible issues. BUG=b:156691665 TEST=make; boots on Kukui BRANCH=kukui Change-Id: Ib4f4866aa26fd9ea797c1b74b6b59349f1898ccd Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41503/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 1b610ed..a2487b4 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -26,8 +26,8 @@ enum { LCM_ID_CHANNEL = 2, /* ID of LCD Module on schematics. */ - RAM_ID_CHANNEL = 3, - SKU_ID_CHANNEL = 4, + RAM_L_ID_CHANNEL = 3, /* Low 4 bits of RAM code */ + RAM_H_ID_CHANNEL = 4, /* High 4 bits of RAM code */ }; static const int ram_voltages[ADC_LEVELS] = { @@ -64,8 +64,8 @@ static const int *adc_voltages[] = { [LCM_ID_CHANNEL] = lcm_voltages, - [RAM_ID_CHANNEL] = ram_voltages, - [SKU_ID_CHANNEL] = ram_voltages, /* SKU ID is sharing RAM voltages. */ + [RAM_L_ID_CHANNEL] = ram_voltages, + [RAM_H_ID_CHANNEL] = ram_voltages, }; static uint32_t get_adc_index(unsigned int channel) @@ -101,7 +101,7 @@ return cached_sku_id; } - /* Quirk for Kukui: All Rev1/Sku0 had incorrectly set SKU_ID=1. */ + /* Quirk for Kukui: All Rev1/Sku0 had incorrectly set SKU ID=1. */ if (CONFIG(BOARD_GOOGLE_KUKUI)) { if (board_id() == 1) { cached_sku_id = 0; @@ -112,10 +112,10 @@ /* * The SKU (later used for device tree matching) is combined from: * ADC2[4bit/H] = straps on LCD module (type of panel). - * ADC4[4bit/L] = SKU ID from board straps. + * EC [4bit/L] = straps on EC SKU ID straps. */ cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | - get_adc_index(SKU_ID_CHANNEL)); + google_chromeec_get_sku_id()); return cached_sku_id; } @@ -124,6 +124,7 @@ static uint32_t cached_ram_code = BOARD_ID_INIT; if (cached_ram_code == BOARD_ID_INIT) - cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + cached_ram_code = (get_adc_index(RAM_H_ID_CHANNEL) << 4 | + get_adc_index(RAM_L_ID_CHANNEL)); return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4f4866aa26fd9ea797c1b74b6b59349f1898ccd Gerrit-Change-Number: 41503 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT
by Morgan Jang (Code Review) 23 Oct '20

23 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46650 ) Change subject: soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT ...................................................................... soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT Set SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button on Copperlake platform. Change-Id: I268c178dfc094299ea6ec239aa1a7c82ccdb0410 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46650/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4a..a1af52f 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -152,7 +152,7 @@ fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | - ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_SLEEP_BUTTON; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; -- To view, visit https://review.coreboot.org/c/coreboot/+/46650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268c178dfc094299ea6ec239aa1a7c82ccdb0410 Gerrit-Change-Number: 46650 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Revert "soc/intel/xeon_sp/skx/: Clean up soc_util.c"
by Marc Jones (Code Review) 23 Oct '20

23 Oct '20

Hello build bot (Jenkins), Jonathan Zhang, Jay Talbott, Stefan Reinauer, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45009 to review the following change. Change subject: Revert "soc/intel/xeon_sp/skx/: Clean up soc_util.c" ...................................................................... Revert "soc/intel/xeon_sp/skx/: Clean up soc_util.c" This reverts commit 985d956833180679bcd8da8c9bbac7522d1f8b8e. Reason for revert: Breaks build. Requires CB:46093 to be applied first. Change-Id: I8dedce025fb6b819406b18974e413693218676d3 --- M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 2 files changed, 79 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45009/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index d641f76..0eac836 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -5,26 +5,34 @@ #include <hob_iiouds.h> #include <hob_memmap.h> +#include <acpi/acpi.h> +#include <soc/util.h> struct iiostack_resource { uint8_t no_of_stacks; STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; +uintptr_t get_tolm(uint32_t bus); +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); +uintptr_t get_cha_mmcfg_base(uint32_t bus); +uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); + +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); void get_iiostack_info(struct iiostack_resource *info); -void xeonsp_init_cpu_config(void); - -void config_reset_cpl3_csrs(void); - -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread); - -int get_platform_thread_count(void); int get_threads_per_package(void); -const struct SystemMemoryMapHob *get_system_memory_map(void); +int get_platform_thread_count(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, + uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); + +const struct SystemMemoryMapHob *get_system_memory_map(void); +void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +void config_reset_cpl3_csrs(void); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 8b29e7f..50f091e 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -17,6 +17,61 @@ #include <soc/util.h> #include <timer.h> +/* + * Get TOLM CSR B0:D5:F0:Offset_d0h + */ +uintptr_t get_tolm(uint32_t bus) +{ + uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TOLM_CSR); + uintptr_t addr = w & 0xfc000000; + printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr); + return addr; +} + +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit) +{ + uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_BASE_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_LIMIT_CSR); + *base = w1 & 0xfff00000; + *limit = wh & 0xfff00000; +} + +/* + * Get MMCFG CSR B1:D29:F1:Offset_C0h + */ +uintptr_t get_cha_mmcfg_base(uint32_t bus) +{ + uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4); + uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26); + printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n", + wl, wh, addr); + return addr; +} + +uint32_t top_of_32bit_ram(void) +{ + uintptr_t mmcfg, tolm; + uint32_t bus0 = 0, bus1 = 0; + uint32_t base = 0, limit = 0; + + get_cpubusnos(&bus0, &bus1, NULL, NULL); + + mmcfg = get_cha_mmcfg_base(bus1); + tolm = get_tolm(bus0); + printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n", + bus0, bus1, mmcfg, tolm); + get_tseg_base_lim(bus0, &base, &limit); + printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit); + + /* We will use TSEG base as the top of DRAM */ + return base; +} /* * +-------------------------+ TOLM @@ -46,7 +101,12 @@ * +-------------------------+ */ -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) +{ + return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset); +} + +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { size_t hob_size; const IIO_UDS *hob; -- To view, visit https://review.coreboot.org/c/coreboot/+/45009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dedce025fb6b819406b18974e413693218676d3 Gerrit-Change-Number: 45009 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/skx: Add missing includes
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46662 ) Change subject: soc/intel/xeon_sp/skx: Add missing includes ...................................................................... soc/intel/xeon_sp/skx: Add missing includes Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed some indirect header inclusions, which resulted in a build failure. Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/cpu.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46662/1 diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb..4324660 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -7,6 +7,7 @@ #include <soc/acpi.h> #include <soc/ramstage.h> #include <soc/soc_util.h> +#include <soc/util.h> struct pci_resource { struct device *dev; diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index ea9f531..bf712c3 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -9,6 +9,7 @@ #include <soc/msr.h> #include <soc/cpu.h> #include <soc/soc_util.h> +#include <soc/util.h> #include <assert.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/46662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0 Gerrit-Change-Number: 46662 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in em100[master]: Update to use upstream version 4.3.10
by Stefan Reinauer (Code Review) 23 Oct '20

23 Oct '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/45537 ) Change subject: Update to use upstream version 4.3.10 ...................................................................... Update to use upstream version 4.3.10 Upstream 4.3.10 is using a different download slot, adjusting the makechips.sh script. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I740885e4773dcbd236d1a645e03b6896bf39c0d1 --- M makechips.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/37/45537/1 diff --git a/makechips.sh b/makechips.sh index fcf0070..8a2d901 100755 --- a/makechips.sh +++ b/makechips.sh @@ -12,7 +12,7 @@ # GNU General Public License for more details. # -URL="https://www.dediprog.com/download/save/78.msi" +URL="https://www.dediprog.com/download/save/1145.msi" VURL="https://www.dediprog.com/download?productCategory=SPI+Flash+Solution&produc…" if ! which curl > /dev/null; then -- To view, visit https://review.coreboot.org/c/em100/+/45537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I740885e4773dcbd236d1a645e03b6896bf39c0d1 Gerrit-Change-Number: 45537 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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