coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/broadwell: Drop reg-script from early SA init
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46339 ) Change subject: soc/intel/broadwell: Drop reg-script from early SA init ...................................................................... soc/intel/broadwell: Drop reg-script from early SA init Haswell does not use reg-script, but does more or less the same thing. Adapt Broadwell to ease the eventual unification with Haswell. Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/romstage/systemagent.c 1 file changed, 21 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46339/1 diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 6f6db62..67e5d8c 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -9,34 +9,35 @@ #include <soc/romstage.h> #include <soc/systemagent.h> -static const struct reg_script systemagent_early_init_script[] = { - REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1), - REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1), - REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1), +static void broadwell_setup_bars(void) +{ + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + + MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; + MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; /* Set C0000-FFFFF to access RAM on both reads and writes */ - REG_PCI_WRITE8(PAM0, 0x30), - REG_PCI_WRITE8(PAM1, 0x33), - REG_PCI_WRITE8(PAM2, 0x33), - REG_PCI_WRITE8(PAM3, 0x33), - REG_PCI_WRITE8(PAM4, 0x33), - REG_PCI_WRITE8(PAM5, 0x33), - REG_PCI_WRITE8(PAM6, 0x33), - - /* Device enable: IGD and Mini-HD */ - REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN), - - REG_SCRIPT_END -}; + pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); + pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); +} void systemagent_early_init(void) { const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); - reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script); + broadwell_setup_bars(); + + /* Device enable: IGD and Mini-HD */ + pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); if (vtd_capable) { /* setup BARs: zeroize top 32 bits; set enable bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04 Gerrit-Change-Number: 46339 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Nick Vaccaro (Code Review) 23 Oct '20

23 Oct '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 23 Oct 2020 17:47:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Furquan Shaikh (Code Review) 23 Oct '20

23 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 8: Code-Review+2 (3 comments) https://review.coreboot.org/c/coreboot/+/45747/7/src/ec/google/chromeec/chi… File src/ec/google/chromeec/chip.h: https://review.coreboot.org/c/coreboot/+/45747/7/src/ec/google/chromeec/chi… PS7, Line 6: #include <stddef.h> #include <device/device.h>? https://review.coreboot.org/c/coreboot/+/45747/8/src/ec/google/chromeec/ec_… File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/45747/8/src/ec/google/chromeec/ec_… PS8, Line 138: for (i = 0; i < num_ports; ++i) { Should there be a check here: if (config->mux_conn[i] == NULL) { printk(BIOS_ERR, "Error: Mux connector info missing for Type-C port #%d\n", i); continue; } https://review.coreboot.org/c/coreboot/+/45747/8/src/ec/google/chromeec/ec_… PS8, Line 146: get_usb_port_references Not for this change, but I think we can use the alias mechanism for usb2/3/4 ports as well so that we don't have to parse the entire tree looking for matching ports. -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 23 Oct 2020 17:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h
by Felix Held (Code Review) 23 Oct '20

23 Oct '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46334 ) Change subject: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h ...................................................................... vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h Remove all typedefs and cleanup references to all structs and enums. BUG=b:159061802 TEST=Boot morphius to shell. Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/svc.c M src/soc/amd/picasso/psp_verstage/vboot_crypto.c M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 4 files changed, 57 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 89e7014..7d0b856 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -70,7 +70,7 @@ static struct { const char *name; struct { - FCH_IO_DEVICE device; + enum fch_io_device device; uint32_t arg0; } args; void (*set_bar)(void *bar); @@ -90,7 +90,7 @@ uintptr_t *map_spi_rom(void) { uintptr_t *addr = NULL; - struct SPIROM_INFO spi = {0}; + struct spirom_info spi = {0}; if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index b847276..acc9c70 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -53,14 +53,14 @@ SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); } -uint32_t svc_get_spi_rom_info(SPIROM_INFO *spi_rom_info) +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) { uint32_t retval = 0; SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); return retval; } -uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_map_fch_dev(enum fch_io_device io_device, uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) { uint32_t retval = 0; @@ -70,7 +70,7 @@ return retval; } -uint32_t svc_unmap_fch_dev(FCH_IO_DEVICE io_device, void *io_device_axi_addr) +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) { uint32_t retval = 0; assert(io_device < FCH_IO_DEVICE_END); @@ -96,7 +96,7 @@ } uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset, DIR_OFFSET_OPERATION operation) + uint32_t *bios_dir_offset, enum dir_offset_operation operation) { uint32_t retval = 0; assert(operation < DIR_OFFSET_OPERATION_MAX); @@ -105,7 +105,7 @@ return retval; } -uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, +uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size) { uint32_t retval = 0; @@ -114,7 +114,7 @@ return retval; } -uint32_t svc_read_timer_val(PSP_TIMER_TYPE type, uint64_t *counter_value) +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) { unsigned int retval = 0; assert(type < PSP_TIMER_TYPE_MAX); @@ -122,7 +122,7 @@ return retval; } -uint32_t svc_reset_system(RESET_TYPE reset_type) +uint32_t svc_reset_system(enum reset_type reset_type) { unsigned int retval = 0; assert(reset_type < RESET_TYPE_MAX); @@ -144,21 +144,21 @@ return retval; } -uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode) +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) { uint32_t retval = 0; SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval); return retval; } -uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *rsa_params) +uint32_t svc_rsa_pkcs_verify(const struct rsapkcs_verify_params *rsa_params) { uint32_t retval = 0; SVC_CALL1(SVC_RSAPKCS_VERIFY, rsa_params, retval); return retval; } -uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param) +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) { uint32_t retval = 0; SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); diff --git a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c index d9364d0..3f7151a 100644 --- a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c @@ -11,7 +11,7 @@ #include <swab.h> #include <vb2_api.h> -static struct SHA_GENERIC_DATA_T sha_op; +static struct sha_generic_data sha_op; static uint32_t sha_op_size_remaining; static uint8_t __attribute__((aligned(32))) sha_hash[64]; @@ -113,7 +113,7 @@ * Since PSP expects everything in LE and *inout is BE array, * we'll use workbuf for temporary buffer for endian conversion. */ - MOD_EXP_PARAMS mod_exp_param; + struct mod_exp_params mod_exp_param; unsigned int key_bytes = key->arrsize * sizeof(uint32_t); uint32_t *sig_swapped = workbuf32; uint32_t *output_buffer = &workbuf32[key->arrsize]; diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 93f987b..c057295 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -60,8 +60,7 @@ #define PSP_INFO_PRODUCTION_SILICON 0x00000002UL #define PSP_INFO_VALID 0x80000000UL -typedef struct MOD_EXP_PARAMS_T -{ +struct mod_exp_params { char *pExponent; // Exponent address unsigned int ExpSize; // Exponent size in bytes char *pModulus; // Modulus address @@ -69,10 +68,9 @@ char *pMessage; // Message address, same size as ModulusSize char *pOutput; // Output address; Must be big enough to hold the // data of ModulusSize -} MOD_EXP_PARAMS; +}; -typedef struct _RSAPSS_VERIFY_PARAMS_T -{ +struct rsapss_verify_params { char *pHash; // Message digest to verify the RSA signature unsigned int HashLen; // hash length in bytes char *pModulus; // Modulus address @@ -80,10 +78,9 @@ char *pExponent; // Exponent address unsigned int ExpSize; // Exponent length in bytes char *pSig; // Signature to be verified, same size as ModulusSize -} RSAPSS_VERIFY_PARAMS; +}; -typedef struct RSAPKCS_VERIFY_PARAMS_T -{ +struct rsapkcs_verify_params { char *pHash; // Message digest to verify the RSA signature unsigned int HashLen; // hash length in bytes char *pModulus; // Modulus address @@ -91,19 +88,18 @@ char *pExponent; // Exponent address unsigned int ExpSize; // Exponent length in bytes char *pSig; // Signature to be verified, same size as ModulusSize -} RSAPKCS_VERIFY_PARAMS; +}; -typedef enum _PSP_BOOT_MODE -{ +enum psp_boot_mode { PSP_BOOT_MODE_S0 = 0x0, PSP_BOOT_MODE_S0i3_RESUME = 0x1, PSP_BOOT_MODE_S3_RESUME = 0x2, PSP_BOOT_MODE_S4 = 0x3, PSP_BOOT_MODE_S5_COLD = 0x4, PSP_BOOT_MODE_S5_WARM = 0x5, -} PSP_BOOT_MODE; +}; -typedef enum FCH_IO_DEVICE { +enum fch_io_device { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, FCH_IO_DEVICE_GPIO, @@ -114,68 +110,61 @@ FCH_IO_DEVICE_IOPORT, FCH_IO_DEVICE_END, -} FCH_IO_DEVICE; +}; /* Svc_UpdatePspBiosDir can be used to GET or SET the PSP or BIOS directory * offsets. This enum is used to specify whether it is a GET or SET operation. */ -typedef enum DIR_OFFSET_OPERATION_E { +enum dir_offset_operation { DIR_OFFSET_GET = 0x0, DIR_OFFSET_SET, DIR_OFFSET_OPERATION_MAX -} DIR_OFFSET_OPERATION; +}; -typedef enum FCH_I2C_CONTROLLER_ID_E -{ +enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_2 = 2, FCH_I2C_CONTROLLER_ID_3 = 3, FCH_I2C_CONTROLLER_ID_4 = 4, FCH_I2C_CONTROLLER_ID_MAX, -} FCH_I2C_CONTROLLER_ID; +}; -typedef enum UAPP_COPYBUF -{ +enum uapp_copybuf { UAPP_COPYBUF_CHROME_WORKBUF = 0x0, UAPP_COPYBUF_MAX = 0x1, -} UAPP_COPYBUF; +}; -typedef struct SPIROM_INFO -{ +struct spirom_info { void *SpiBiosSysHubBase; void *SpiBiosSmnBase; uint32_t SpiBiosSize; -} SPIROM_INFO; +}; -typedef enum PSP_TIMER_TYPE { +enum psp_timer_type { PSP_TIMER_TYPE_CHRONO = 0, PSP_TIMER_TYPE_RTC = 1, PSP_TIMER_TYPE_MAX = 2, -} PSP_TIMER_TYPE; +}; -typedef enum RESET_TYPE -{ +enum reset_type { RESET_TYPE_COLD = 0, RESET_TYPE_WARM = 1, RESET_TYPE_MAX = 2, -} RESET_TYPE; +}; /* SHA types same as ccp SHA type in crypto.h */ -typedef enum SHA_TYPE -{ +enum sha_type { SHA_TYPE_256, SHA_TYPE_512 -} SHA_TYPE; +}; /* All SHA operation supported */ -typedef enum SHA_OPERATION_MODE -{ +enum sha_operation_mode { SHA_GENERIC -} SHA_OPERATION_MODE; +}; /* SHA Supported Data Structures */ -typedef struct SHA_GENERIC_DATA_T -{ - SHA_TYPE SHAType; +struct sha_generic_data { + enum sha_type SHAType; uint8_t *Data; uint32_t DataLen; uint32_t DataMemType; @@ -185,7 +174,7 @@ uint32_t IntermediateMsgLen; uint32_t Init; uint32_t Eom; -} SHA_GENERIC_DATA; +}; /* * Exit to the main Boot Loader. This does not return back to user application. @@ -231,7 +220,7 @@ */ uint32_t svc_wait_10ns_multiple(uint32_t multiple); -/* Description - Returns the current boot mode from the type PSP_BOOT_MODE found in +/* Description - Returns the current boot mode from the enum psp_boot_mode found in * bl_public.h. * * Inputs - boot_mode - Output parameter passed in R0 @@ -261,7 +250,7 @@ * * Return value: BL_OK or error code */ -uint32_t svc_get_spi_rom_info(SPIROM_INFO *spi_rom_info); +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info); /* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...) * @@ -273,7 +262,7 @@ * * Return value: BL_OK or error code */ -uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_map_fch_dev(enum fch_io_device io_device, uint32_t arg1, uint32_t arg2, void **io_device_axi_addr); /* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice() @@ -284,7 +273,7 @@ * * Return value: BL_OK or error code */ -uint32_t svc_unmap_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr); /* Map the SPIROM FLASH device address space @@ -324,7 +313,7 @@ * Return value: BL_OK or error code */ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset, DIR_OFFSET_OPERATION operation); + uint32_t *bios_dir_offset, enum dir_offset_operation operation); /* Copies the data that is shared by verstage to the PSP BL owned memory * @@ -333,7 +322,7 @@ * address - Address in UAPP controlled/owned memory * size - Total size of memory to copy (max 16Kbytes) */ -uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, +uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size); /* @@ -345,7 +334,7 @@ * counter_value - [out] return the raw counter value read from * RTC or CHRONO_LO/HI counter register */ -uint32_t svc_read_timer_val( PSP_TIMER_TYPE type, uint64_t *counter_value ); +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value ); /* * Reset the system @@ -353,7 +342,7 @@ * Parameters: * reset_type - Cold or Warm reset */ -uint32_t svc_reset_system(RESET_TYPE reset_type); +uint32_t svc_reset_system(enum reset_type reset_type); /* * Write postcode to Port-80 @@ -374,27 +363,27 @@ /* * Generic SHA call for SHA, SHA_OTP, SHA_HMAC */ -uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode); +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode); /* * RSA PSS Verification of signature and data * * Parameters: - * RSAPSS_VERIFY_PARAMS - Pointer to RSA PSS parameters + * rsapss_verify_params - Pointer to RSA PSS parameters * * Return value: BL_OK or error code */ -uint32_t svc_rsa_pss_verify(const RSAPSS_VERIFY_PARAMS *params); +uint32_t svc_rsa_pss_verify(const struct rsapss_verify_params *params); /* * RSA PKCS Verification of signature and data * * Parameters: - * RSAPKCS_VERIFY_PARAMS - Pointer to RSA PKCS parameters + * struct rsapkcs_verify_params - Pointer to RSA PKCS parameters * * Return value: BL_OK or error code */ -uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); +uint32_t svc_rsa_pkcs_verify(const struct rsapkcs_verify_params *params); /* Calculate ModEx * @@ -403,7 +392,7 @@ * * Return value: BL_OK or error code */ -uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param); +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Gerrit-Change-Number: 46334 Gerrit-PatchSet: 5 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: update telemetry settings for morphius
by Kevin Chiu (Code Review) 23 Oct '20

23 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46655 ) Change subject: mb/google/zork: update telemetry settings for morphius ...................................................................... mb/google/zork: update telemetry settings for morphius Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD Slope: 62852 -> 62641 SOC Slope: 28022 -> 28333 BUG=b:170531252 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0 --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46655/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 66b371b..e04a62e 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -16,9 +16,9 @@ register "sustained_power_limit" = "12000" #mw register "thermctl_limit" = "100" #degrees C - register "telemetry_vddcr_vdd_slope" = "62852" #mA + register "telemetry_vddcr_vdd_slope" = "62641" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28022" #mA + register "telemetry_vddcr_soc_slope" = "28333" #mA register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode -- To view, visit https://review.coreboot.org/c/coreboot/+/46655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0 Gerrit-Change-Number: 46655 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/google/zork/woomax: Adjust disconnect threshold
by Rob Barnes (Code Review) 23 Oct '20

23 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46601 ) Change subject: mb/google/zork/woomax: Adjust disconnect threshold ...................................................................... mb/google/zork/woomax: Adjust disconnect threshold The disconnect voltage needs to be adjusted up because the HS DC voltage level is 0xF. BUG=b:170879690 TEST=Servo_v4 USB hub functions BRANCH=zork Change-Id: If8662015a45c57e457b4593e55af888084842f58 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/woomax/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46601/1 diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 19d66fc..e9d66f9 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -24,7 +24,7 @@ # End : OPN Performance Configuration #USB 2.0 strength register "usb_2_port_tune_params[0]" = "{ - .com_pds_tune = 0x03, + .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, @@ -36,7 +36,7 @@ }" register "usb_2_port_tune_params[3]" = "{ - .com_pds_tune = 0x03, + .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, -- To view, visit https://review.coreboot.org/c/coreboot/+/46601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8662015a45c57e457b4593e55af888084842f58 Gerrit-Change-Number: 46601 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Deepika Punyamurtula (Code Review) 23 Oct '20

23 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 63: 15000 Yes, this looks like a typo. These need to be different. A couple of more comments 1)for the pl2 since it is different from the default 60W, the register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl2_override = 60,}" needs to be added. 2) Can you also add the tcc_offset="8" as it is different from the default of 10C? Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 23 Oct 2020 16:10:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: Update the flash ROM layout for RW regions
by Karthik Ramasubramanian (Code Review) 23 Oct '20

23 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46569 ) Change subject: mb/google/dedede: Update the flash ROM layout for RW regions ...................................................................... mb/google/dedede: Update the flash ROM layout for RW regions * Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to RW_LEGACY region so that it grows to 1 MiB. * Remove VBLOCK_DEV region which is not used. * Re-size the ELOG region to 4 KiB since that is the maximum size of the ELOG mirror buffer. * Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that size is used in those regions. * Resize SHARED_DATA region to 4 KiB since no more than that size is used in that region. * Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB. BUG=b:167943992, b:167498108 TEST=Build and boot to OS in Drawlat. Ensure that the firmware test setup and flash map test are successful. Ensure that the event logs are synced properly between reboots. Ensure that the suspend/resume sequence is working fine. Ensure that the ChromeOS firmware update completes successfully for the boot image with updated flash map and the system boots fine after the update. Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd 1 file changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46569/1 diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 09b2abc..0e21c4c 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -4,29 +4,28 @@ SI_ME@0x1000 0x380000 } SI_BIOS@0x381000 0xc7f000 { - RW_LEGACY(CBFS)@0x0 0x1000 - RW_SECTION_A@0x1000 0x420000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x40ffc0 - RW_FWID_A@0x41ffc0 0x40 + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x3a27c0 + RW_FWID_A@0x3a47c0 0x40 } - RW_SECTION_B@0x421000 0x420000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x40ffc0 - RW_FWID_B@0x41ffc0 0x40 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x3a27c0 + RW_FWID_B@0x3a47c0 0x40 } - RW_MISC@0x841000 0x3e000 { + RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x3000 - RW_SHARED@0x33000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x37000 0x2000 - RW_NVRAM(PRESERVE)@0x39000 0x5000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } # Make WP_RO region align with SPI vendor # memory protected range specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/46569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838 Gerrit-Change-Number: 46569 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: mb/google/dedede/var/drawcia: Add MIPI camera support
by Chen Wisley (Code Review) 23 Oct '20

23 Oct '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44939 ) Change subject: mb/google/dedede/var/drawcia: Add MIPI camera support ...................................................................... mb/google/dedede/var/drawcia: Add MIPI camera support 1. enable IPU 2. enable VARIANT_HAS_CAMERA_ACPI 3. add VCM/NVM asl code BUG=b:163879470 TEST=follow steps on issue tracker to grap picture manually. Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 6 files changed, 455 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44939/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 40738a0..5924ac1 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -20,6 +20,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" @@ -27,6 +28,7 @@ select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_MADOO bool "-> Madoo" diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..1e9218e --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/cam1.asl @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + If ((STA == Zero)) + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + /* Assert Reset */ + PON() + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA = 1 + } + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + If ((STA == One)) + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + POFF() + STA = 0 + } + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x02) + { + 0x15752A00, + 0xABA9500 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device(VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + + Name (_UID, 0x00) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM1 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } + + Device (NVM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + + Name (_UID, 0x01) /* _UID: Unique ID */ + + Name (_DDN, "AT24 EEPROM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status*/ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM1 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x05) + { + Package (0x02) + { + "size", + 0x0400 + }, + + Package (0x02) + { + "pagesize", + One + }, + + Package (0x02) + { + "read-only", + One + }, + + Package (0x02) + { + "address-width", + 0x08 + }, + + Package (0x02) + { + "compatible", + "atmel,24c08" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl new file mode 100644 index 0000000..48650c9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/camera.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..7b38702 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..34c3d4b --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee95332..809ce6c 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -47,6 +47,7 @@ register "tcc_offset" = "20" # TCC of 85C device domain 0 on + device pci 05.0 on end # IPU - MIPI Camera device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/44939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Gerrit-Change-Number: 44939 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

10 48

Change in coreboot[master]: soc/intel/broadwell: Guard MCHBAR macro parameters
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46336 ) Change subject: soc/intel/broadwell: Guard MCHBAR macro parameters ...................................................................... soc/intel/broadwell: Guard MCHBAR macro parameters Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/systemagent.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/46336/1 diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 52d386b..6f475a5 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -80,9 +80,9 @@ /* MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR_PEI_VERSION 0x5034 -- To view, visit https://review.coreboot.org/c/coreboot/+/46336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e Gerrit-Change-Number: 46336 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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