coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46357 ) Change subject: soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c ...................................................................... soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c Other Intel northbridges have this function in this file. Change-Id: I9f084e760ec438d662484455212b5c40a8448928 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c 2 files changed, 14 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46357/1 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index e4c787a..f7e58af 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -3,6 +3,7 @@ /* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ +#include <arch/romstage.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <device/pci.h> @@ -43,3 +44,16 @@ *start = tseg; *size = bgsm - tseg; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40..83e5b73 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,19 +16,6 @@ #include <soc/romstage.h> #include <soc/spi.h> -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); -} - /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f084e760ec438d662484455212b5c40a8448928 Gerrit-Change-Number: 46357 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Drop reg-script usage from bootblock PCH init
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46352 ) Change subject: soc/intel/broadwell: Drop reg-script usage from bootblock PCH init ...................................................................... soc/intel/broadwell: Drop reg-script usage from bootblock PCH init Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/bootblock/pch.c 1 file changed, 50 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46352/1 diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 27d9a3e..14a5061 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -7,7 +7,6 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/spi.h> -#include <reg_script.h> #include <soc/pm.h> #include <soc/romstage.h> #include <southbridge/intel/common/early_spi.h> @@ -46,49 +45,61 @@ SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } -const struct reg_script pch_early_init_script[] = { - /* Setup southbridge BARs */ - REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), - REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), - REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), - REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), - REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), +static void pch_enable_bars(void) +{ + /* Set up southbridge BARs */ + pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + + pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); + + pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN); + + pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN); /* Set COM1/COM2 decode range */ - REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), - /* Enable legacy decode ranges */ - REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | - COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), - - /* Enable IOAPIC */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), - /* Read back for posted write */ - REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), - - /* Set HPET address and enable it */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), - /* Read back for posted write */ - REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), - /* Enable HPET to start counter */ - REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), - - /* Disable reset */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), - /* TCO timer halt */ - REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), - - /* Enable upper 128 bytes of CMOS */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), - - /* Disable unused device (always) */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), - - REG_SCRIPT_END -}; + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010); +} static void pch_early_lpc(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); + pch_enable_bars(); + + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_config); + + /* Enable IOAPIC */ + RCBA16(OIC) = 0x0100; + + /* Read back for posted write */ + (void) RCBA16(OIC); + + /* Set HPET address and enable it */ + RCBA32_AND_OR(HPTC, ~3, 1 << 7); + + /* Read it back to stick. It's affected by posted write syndrome. */ + RCBA32(HPTC); + + /* Enable HPET to start counter */ + setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0); + + /* Disable reset */ + RCBA32_OR(GCS, 1 << 5); + + /* TCO timer halt */ + u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); + reg16 |= TCO_TMR_HLT; + outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); + + /* Enable upper 128 bytes of CMOS */ + RCBA32_OR(RC, 1 << 2); + + /* Disable unused device (always) */ + RCBA32_OR(FD, PCH_DISABLE_ALWAYS); } void bootblock_early_southbridge_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/46352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a Gerrit-Change-Number: 46352 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Define RCBA register LCAP
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46340 ) Change subject: soc/intel/broadwell: Define RCBA register LCAP ...................................................................... soc/intel/broadwell: Define RCBA register LCAP This register has a name. Use it. Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/include/soc/rcba.h 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46340/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 5539f61..a13c214 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -97,8 +97,8 @@ /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); - /* Read+Write the following register */ - RCBA32(0x21a4) = RCBA32(0x21a4); + /* Read+Write this R/WO register */ + RCBA32(LCAP) = RCBA32(LCAP); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h index 3bacb9d..0c63eb2 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/soc/intel/broadwell/include/soc/rcba.h @@ -48,6 +48,8 @@ #define PIRQG 6 #define PIRQH 7 +#define LCAP 0x21a4 + /* IO Buffer Programming */ #define IOBPIRI 0x2330 #define IOBPD 0x2334 -- To view, visit https://review.coreboot.org/c/coreboot/+/46340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81 Gerrit-Change-Number: 46340 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/broadwell/finalize.c: Use register names
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46338 ) Change subject: soc/intel/broadwell/finalize.c: Use register names ...................................................................... soc/intel/broadwell/finalize.c: Use register names Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ida1266f52fcc06577bd876f2cf3e3324ced6ab9d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46338/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 5601800..5539f61 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -25,17 +25,17 @@ { struct device *host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); - pci_or_config16(host_bridge, 0x50, 1 << 0); /* GGC */ - pci_or_config32(host_bridge, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(host_bridge, 0x78, 1 << 10); /* ME */ - pci_or_config32(host_bridge, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(host_bridge, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(host_bridge, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(host_bridge, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(host_bridge, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(host_bridge, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(host_bridge, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(host_bridge, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(host_bridge, GGC, 1 << 0); + pci_or_config32(host_bridge, DPR, 1 << 0); + pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10); + pci_or_config32(host_bridge, REMAPBASE, 1 << 0); + pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0); + pci_or_config32(host_bridge, TOM, 1 << 0); + pci_or_config32(host_bridge, TOUUD, 1 << 0); + pci_or_config32(host_bridge, BDSM, 1 << 0); + pci_or_config32(host_bridge, BGSM, 1 << 0); + pci_or_config32(host_bridge, TSEG, 1 << 0); + pci_or_config32(host_bridge, TOLUD, 1 << 0); MCHBAR32(MMIO_PAVP_MSG) |= 1 << 0; MCHBAR32(SAPMCTL) |= 1 << 31; -- To view, visit https://review.coreboot.org/c/coreboot/+/46338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1266f52fcc06577bd876f2cf3e3324ced6ab9d Gerrit-Change-Number: 46338 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Sort SA registers in ascending order
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46337 ) Change subject: soc/intel/broadwell: Sort SA registers in ascending order ...................................................................... soc/intel/broadwell: Sort SA registers in ascending order Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/systemagent.h 1 file changed, 41 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46337/1 diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 6f475a5..5a52590 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -29,8 +29,6 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) @@ -45,6 +43,11 @@ #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define PAM0 0x80 #define PAM1 0x81 @@ -60,14 +63,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2) -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define REMAPBASE 0x90 /* Remap base. */ #define REMAPLIMIT 0x98 /* Remap limit. */ #define TOM 0xa0 /* Top of DRAM in memory controller space. */ @@ -78,6 +74,13 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */ #define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) @@ -88,7 +91,6 @@ #define MC_LOCK 0x50fc -#define BIOS_RESET_CPL 0x5da8 #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 @@ -99,11 +101,38 @@ #define PCU_DDR_PTM_CTL 0x5880 -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + +#define BIOS_RESET_CPL 0x5da8 + #define SAPMCTL 0x5f00 #define HDAUDRID 0x6008 @@ -115,29 +144,6 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 -#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* System Agent identification */ u8 systemagent_revision(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Gerrit-Change-Number: 46337 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Drop reg-script to finalize SA
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46525 ) Change subject: soc/intel/broadwell: Drop reg-script to finalize SA ...................................................................... soc/intel/broadwell: Drop reg-script to finalize SA There's no need to use reg-script to do this. Since Haswell does not use reg-script, drop it here to ease comparisons between both platforms. Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c 1 file changed, 37 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/46525/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 5e7e4c6..fe3dfb6 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,6 +3,8 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <device/device.h> +#include <device/pci_ops.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> @@ -19,29 +21,41 @@ * Document Number 535094 * Revision 2.2.0, August 2014 */ -const struct reg_script system_agent_finalize_script[] = { - REG_PCI_OR16(0x50, 1 << 0), /* GGC */ - REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ - REG_PCI_OR32(0x78, 1 << 10), /* ME */ - REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */ - REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */ - REG_PCI_OR32(0xa0, 1 << 0), /* TOM */ - REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */ - REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */ - REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ - REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ - REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ +static void broadwell_systemagent_finalize(void) +{ + struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); - REG_SCRIPT_END -}; + pci_or_config16(host_bridge, 0x50, 1 << 0); /* GGC */ + pci_or_config32(host_bridge, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(host_bridge, 0x78, 1 << 10); /* ME */ + pci_or_config32(host_bridge, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(host_bridge, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(host_bridge, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(host_bridge, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(host_bridge, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(host_bridge, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(host_bridge, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(host_bridge, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32(0x5500) |= 1 << 0; + MCHBAR32(0x5f00) |= 1 << 31; + MCHBAR32(0x6020) |= 1 << 0; + MCHBAR32(0x63fc) |= 1 << 0; + MCHBAR32(0x6800) |= 1 << 31; + MCHBAR32(0x7000) |= 1 << 31; + MCHBAR32(0x77fc) |= 1 << 0; + + /* Memory Controller Lockdown */ + MCHBAR8(0x50fc) = 0x8f; + + /* Read+write the following */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); + + /* This is a lock bit, but does not appear in the SA locking sequence */ + MCHBAR32(0x5880) |= 1 << 5; +} const struct reg_script pch_finalize_script[] = { #if !CONFIG(EM100PRO_SPI_CONSOLE) @@ -73,19 +87,9 @@ static void broadwell_finalize(void *unused) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Finalizing chipset.\n"); - reg_script_run_on_dev(sa_dev, system_agent_finalize_script); - - /* Read+Write the following registers */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); - - /* This is a lock bit, but does not appear in the SA locking sequence */ - MCHBAR32(0x5880) |= 1 << 5; + broadwell_systemagent_finalize(); spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); -- To view, visit https://review.coreboot.org/c/coreboot/+/46525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6 Gerrit-Change-Number: 46525 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: nb/intel/haswell/raminit.c: Clean up local variables
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46363 ) Change subject: nb/intel/haswell/raminit.c: Clean up local variables ...................................................................... nb/intel/haswell/raminit.c: Clean up local variables Remove unnecessary arrays, use unsigned types for non-negative values and constify where possible. Also define NUM_CHANNELS and NUM_SLOTS. Change-Id: Ie4eb79d9c48194538c0ee41dca48ea32798ad8c6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 13 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46363/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 7fd6b3f..5a39e60 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -61,12 +61,9 @@ /* Print out the memory controller configuration, as per the values in its registers. */ static void report_memory_config(void) { - u32 addr_decoder_common, addr_decode_chan[2]; int i; - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1)); + const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -76,8 +73,8 @@ (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_chan); i++) { - u32 ch_conf = addr_decode_chan[i]; + for (i = 0; i < NUM_CHANNELS; i++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); @@ -215,10 +212,9 @@ void setup_sdram_meminfo(struct pei_data *pei_data) { - u32 addr_decode_ch[2]; struct memory_info *mem_info; struct dimm_info *dimm; - int ddr_frequency, dimm_size, ch, d_num; + int dimm_size, ch, d_num; int dimm_cnt = 0; mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); @@ -227,16 +223,13 @@ memset(mem_info, 0, sizeof(struct memory_info)); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); + const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; - ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; - - for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { - u32 ch_conf = addr_decode_ch[ch]; + for (ch = 0; ch < NUM_CHANNELS; ch++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); /* DIMMs A/B */ - for (d_num = 0; d_num < 2; d_num++) { - dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; + for (d_num = 0; d_num < NUM_SLOTS; d_num++) { + const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; if (dimm_size) { dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 60e16e0..96d08bf 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -3,6 +3,10 @@ #ifndef __HASWELL_REGISTERS_MCHBAR_H__ #define __HASWELL_REGISTERS_MCHBAR_H__ +/* Memory controller characteristics */ +#define NUM_CHANNELS 2 +#define NUM_SLOTS 2 + /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_DIMM(ch) (0x5004 + (ch) * 4) -- To view, visit https://review.coreboot.org/c/coreboot/+/46363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4eb79d9c48194538c0ee41dca48ea32798ad8c6 Gerrit-Change-Number: 46363 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/broadwell: Drop reg-script for SA lockdown
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46324 ) Change subject: soc/intel/broadwell: Drop reg-script for SA lockdown ...................................................................... soc/intel/broadwell: Drop reg-script for SA lockdown We can just use proper code instead. Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/finalize.c 1 file changed, 25 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/1 diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index bec62fb..1c5423c 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,6 +3,8 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <device/device.h> +#include <device/pci_ops.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> @@ -13,33 +15,6 @@ #include <soc/systemagent.h> #include <southbridge/intel/common/spi.h> -const struct reg_script system_agent_finalize_script[] = { - REG_PCI_OR16(0x50, 1 << 0), /* GGC */ - REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ - REG_PCI_OR32(0x78, 1 << 10), /* ME */ - REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */ - REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */ - REG_PCI_OR32(0xa0, 1 << 0), /* TOM */ - REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */ - REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */ - REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ - REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ - REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), - REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ - - REG_SCRIPT_END -}; - const struct reg_script pch_finalize_script[] = { #if !CONFIG(SPI_CONSOLE) /* Lock SPIBAR */ @@ -74,7 +49,29 @@ printk(BIOS_DEBUG, "Finalizing chipset.\n"); - reg_script_run_on_dev(sa_dev, system_agent_finalize_script); + pci_or_config16(sa_dev, 0x50, 1 << 0); /* GGC */ + pci_or_config32(sa_dev, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(sa_dev, 0x78, 1 << 10); /* ME */ + pci_or_config32(sa_dev, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(sa_dev, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(sa_dev, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(sa_dev, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(sa_dev, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(sa_dev, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(sa_dev, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(sa_dev, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32(0x5500) |= (1 << 0); /* PAVP */ + MCHBAR32(0x5f00) |= (1 << 31); /* SA PM */ + MCHBAR32(0x6020) |= (1 << 0); /* UMA GFX */ + MCHBAR32(0x63fc) |= (1 << 0); /* VTDTRK */ + MCHBAR32(0x6800) |= (1 << 31); + MCHBAR32(0x7000) |= (1 << 31); + MCHBAR32(0x7ffc) |= (1 << 0); + MCHBAR32(0x5880) |= (1 << 5); /* DDR PTM */ + + /* Memory Controller Lockdown */ + MCHBAR8(0x50fc) = 0x8f; spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); -- To view, visit https://review.coreboot.org/c/coreboot/+/46324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Gerrit-Change-Number: 46324 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 21

Change in coreboot[master]: sb/intel/lynxpoint: Drop space after casts
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46528 ) Change subject: sb/intel/lynxpoint: Drop space after casts ...................................................................... sb/intel/lynxpoint: Drop space after casts Casts can be considered unary operators, so drop the space. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46528/1 diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..ce1b109 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -14,7 +14,7 @@ acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); /* fill out header fields */ memcpy(header->signature, "HPET", 4); @@ -37,7 +37,7 @@ hpet->min_tick = 0x0080; header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); + acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) @@ -66,7 +66,7 @@ memcpy(&ssdt->asl_compiler_id, ASLC, 4); ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 956d1d2..6a5dd40 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -108,7 +108,7 @@ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); /* Mainboard RCBA settings */ mainboard_config_rcba(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fad83b1..a161087 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -715,7 +715,7 @@ /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)gnvs); acpigen_pop_len(); } } @@ -748,7 +748,7 @@ */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; + hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = acpi_align_current(current); acpi_create_intel_hpet(hpet); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 57824df..308d3c3 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -149,8 +149,8 @@ write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x03, config->sata_port_map); - (void) read32(abar + 0x03); /* Read back 1 */ - (void) read32(abar + 0x03); /* Read back 2 */ + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x09); /* Enable DEVSLP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3 Gerrit-Change-Number: 46528 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: haswell/broadwell: Fix `BLCK` typo
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46373 ) Change subject: haswell/broadwell: Fix `BLCK` typo ...................................................................... haswell/broadwell: Fix `BLCK` typo Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/soc/intel/broadwell/cpu.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46373/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index ac5dec6..d08f251 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,8 +207,8 @@ return ult; } -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +247,7 @@ err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -259,7 +259,7 @@ return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02..e866136 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@ err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -77,7 +77,7 @@ return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Gerrit-Change-Number: 46373 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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