coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skylake: Fix NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 24 Oct '20

24 Oct '20

Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45010 to look at the new patch set (#3). Change subject: soc/intel/skylake: Fix NHLT_PDM_DEV definition ...................................................................... soc/intel/skylake: Fix NHLT_PDM_DEV definition According to the NHLT specification[1], PDM is defined as "1" on Kabylake based platforms. coreboot sets it to "0" on all platforms. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/nhlt/dmic.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45010/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Fix NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 24 Oct '20

24 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45010 ) Change subject: soc/intel/skylake: Fix NHLT_PDM_DEV definition ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Oct 2020 02:33:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Michael Niewöhner (Code Review) 24 Oct '20

24 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/46465/16/src/acpi/acpigen.c File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/46465/16/src/acpi/acpigen.c@1588 PS16, Line 1588: acpigen_emit_namestring("\\_SB.CP00.GCPC"); > Seems alright though an approach like the following approach on hard-coding might be easier to swall […] Thanks, that looks reasonable -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 16 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Oct 2020 01:26:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: temp
by Jonathan Zhang (Code Review) 24 Oct '20

24 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46712 ) Change subject: temp ...................................................................... temp Change-Id: Ieb7ec255bb0ca528dad031b898643f94aeddb37f --- M src/mainboard/ocp/deltalake/romstage.c 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46712/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index aeb451f..f0cdd3d 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -62,7 +62,8 @@ /* * UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark. - * Following code is effective when MemRefreshWaterMark patch is added to FSP. + * Following code is effective when MemRefreshWaterMark patch is added to FSP + * and when corresponding VPD variable is set. */ if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { val = (uint8_t)atol(val_str); @@ -73,11 +74,6 @@ } printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); mupd->FspmConfig.UnusedUpdSpace0[0] = val; - } else { - printk(BIOS_INFO, "Not able to get VPD %s, default set " - "MemRefreshWatermark to %d\n", FSPM_MEMREFRESHWATERMARK, - FSPM_MEMREFRESHWATERMARK_DEFAULT); - mupd->FspmConfig.UnusedUpdSpace0[0] = FSPM_MEMREFRESHWATERMARK_DEFAULT; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7ec255bb0ca528dad031b898643f94aeddb37f Gerrit-Change-Number: 46712 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Deepika Punyamurtula (Code Review) 24 Oct '20

24 Oct '20

Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 10: register "policies.active" = "{ : [0] = {.target = DPTF_CPU, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [1] = {.target = DPTF_TEMP_SENSOR_0, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [2] = {.target = DPTF_TEMP_SENSOR_1, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [3] = {.target = DPTF_TEMP_SENSOR_2, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [4] = {.target = DPTF_TEMP_SENSOR_3, : .thresholds = {TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" I believe this can be changed to register "policies.active" = "{ [0] = {.target = DPTF_TEMP_SENSOR_3, .thresholds = {TEMP_PCT(57, 90), TEMP_PCT(47, 80), TEMP_PCT(40, 70), TEMP_PCT(36, 60), TEMP_PCT(34, 50), TEMP_PCT(30, 40),}}}" https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 53: 105 Is this supposed to be 100 as shared in the report on the bug? -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 23 Oct 2020 23:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Matt Delco (Code Review) 24 Oct '20

24 Oct '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 16: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46465/16/src/acpi/acpigen.c File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/46465/16/src/acpi/acpigen.c@1588 PS16, Line 1588: acpigen_emit_namestring("\\_SB.CP00.GCPC"); Seems alright though an approach like the following approach on hard-coding might be easier to swallow (while being within reason for some compilers to compute at build-time instead of run-time). #define CPPC_PACKAGE_NAME "GCPC" // acpigen_write_CPPC_package() acpigen_write_name(CPPC_PACKAGE_NAME); // acpigen_write_CPPC_method() char pscope[16]; snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 16 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 22:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: add support for base address bigger than 4GB
by Jonathan Zhang (Code Review) 24 Oct '20

24 Oct '20

Hello Marc Jones, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46435 to review the following change. Change subject: cpu/x86/mtrr: add support for base address bigger than 4GB ...................................................................... cpu/x86/mtrr: add support for base address bigger than 4GB On DeltaLake server, there are following entry in MTRR address space: 0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0 The base address (after 4k page size adjustment) cannot be held in uint32_t. This results incorrect MTRR register setup. As the consequence UEFI forum FWTS reports following critical error: Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached. Change appropriate variables' data type from uint32_t to uint64_t. Add fls64() to find least significant bit set in a 64-bit word. Right now a stop-gap method is used. The 64-bit assembly command causes compilation error. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 --- M src/cpu/x86/mtrr/mtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 25 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46435/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7..27384cc 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -121,12 +121,12 @@ #define MTRR_ALGO_SHIFT (8) #define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1) -static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_base_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_base(r)); } -static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_end_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } @@ -402,7 +402,7 @@ } static void prep_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { struct var_mtrr_regs *regs; resource_t rbase; @@ -444,15 +444,30 @@ regs->mask.hi = rsize >> 32; } +/* fls64: find least significant bit set in a 64-bit word*/ +static uint32_t fls64(uint64_t x) +{ + if (x == 0) return 0; + uint32_t pos = 0; + while (!(x & 1)) { + x >>= 1; + ++pos; + } + return pos; +} + static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { while (size != 0) { uint32_t addr_lsb; uint32_t size_msb; - uint32_t mtrr_size; + uint64_t mtrr_size; - addr_lsb = fls(base); + if (base > 0x100000000) + addr_lsb = fls64(base); + else + addr_lsb = fls(base); size_msb = fms(size); /* All MTRR entries need to have their base aligned to the mask @@ -531,7 +546,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, struct range_entry *r) { - uint32_t a1, a2, b1, b2; + uint64_t a1, a2, b1, b2; int mtrr_type, carve_hole; /* @@ -671,6 +686,8 @@ wb_deftype_count += var_state.mtrr_index; } } + printk(BIOS_DEBUG, "%s %d, uc_deftype_count: %d, wb_deftype_count: %d\n", __func__, __LINE__, uc_deftype_count, wb_deftype_count); + *num_def_wb_mtrrs = wb_deftype_count; *num_def_uc_mtrrs = uc_deftype_count; } diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301c..1497387 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -173,6 +173,7 @@ "1:" : "=r" (r) : "mr" (x)); return r; } + #endif /* !defined(__ASSEMBLER__) */ /* Align up/down to next power of 2, suitable for assembler -- To view, visit https://review.coreboot.org/c/coreboot/+/46435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 Gerrit-Change-Number: 46435 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 24 Oct '20

24 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 24: (1 comment) https://review.coreboot.org/c/coreboot/+/46274/22/src/include/cpu/intel/msr… File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/46274/22/src/include/cpu/intel/msr… PS22, Line 12: #define MSR_PIC_MSG_CONTROL 0x2e > You missed these: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 24 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 22:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 24 Oct '20

24 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45747 to look at the new patch set (#11). Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 --- M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/tigerlake/pmc.c 4 files changed, 17 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45747/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 24 Oct '20

24 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45747/9/src/ec/google/chromeec/ec_… File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/45747/9/src/ec/google/chromeec/ec_… PS9, Line 122: int num_ports; missed this one in #9 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 23 Oct 2020 22:12:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020