coreboot-gerrit October 2020

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Change in coreboot[master]: nb/intel/haswell/early_init.c: Remove invalid register writes
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46683 ) Change subject: nb/intel/haswell/early_init.c: Remove invalid register writes ...................................................................... nb/intel/haswell/early_init.c: Remove invalid register writes MRC overwrites the value of SSKPD and register 0x6120 is reserved. Tested on Asrock B85M Pro4, still boots. Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/early_init.c 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46683/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 79cc277..a0e4211 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -146,16 +146,6 @@ reg32 = MCHBAR32(SAPMCTL); MCHBAR32(SAPMCTL) = reg32 | 1; - /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(SSKPD + 4); - reg32 |= (1UL << 31); - MCHBAR32(SSKPD + 4) = reg32; - - /* VLW (Virtual Legacy Wire?) */ - reg32 = MCHBAR32(0x6120); - reg32 &= ~(1 << 0); - MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); MCHBAR32(INTRDIRCTL) = reg32; -- To view, visit https://review.coreboot.org/c/coreboot/+/46683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3 Gerrit-Change-Number: 46683 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Align with Broadwell
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46682 ) Change subject: nb/intel/haswell/finalize.c: Align with Broadwell ...................................................................... nb/intel/haswell/finalize.c: Align with Broadwell Reorder register writes to match the locking order in Broadwell. Tested on Asrock B85M Pro4, still boots and registers are still locked. Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46682/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 22f9862..1600a42 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,12 +22,12 @@ MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); -- To view, visit https://review.coreboot.org/c/coreboot/+/46682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77 Gerrit-Change-Number: 46682 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Align MC locking with Broadwell
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46681 ) Change subject: nb/intel/haswell/finalize.c: Align MC locking with Broadwell ...................................................................... nb/intel/haswell/finalize.c: Align MC locking with Broadwell Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down. Tested on Asrock B85M Pro4, still boots and register is still locked. Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46681/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1c83110..22f9862 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,6 +17,9 @@ pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); + /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ @@ -26,9 +29,6 @@ MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; - /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); -- To view, visit https://review.coreboot.org/c/coreboot/+/46681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Gerrit-Change-Number: 46681 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Lock down MC ARB register
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46680 ) Change subject: nb/intel/haswell/finalize.c: Lock down MC ARB register ...................................................................... nb/intel/haswell/finalize.c: Lock down MC ARB register The Haswell System Agent BIOS Spec revision 0.6.0 indicates this register needs to be locked, and Broadwell already locks it. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46680/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index efbaf68..1c83110 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -24,6 +24,7 @@ MCHBAR32_OR(REQLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); + MCHBAR32_OR(MCARBLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index bd99cee..97ae433 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -47,5 +47,6 @@ #define REQLIM 0x6800 #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc +#define MCARBLCK 0x7ffc #endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b Gerrit-Change-Number: 46680 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Lock PCU DDR PTM
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46679 ) Change subject: nb/intel/haswell/finalize.c: Lock PCU DDR PTM ...................................................................... nb/intel/haswell/finalize.c: Lock PCU DDR PTM This register has a lock bit. The Haswell System Agent BIOS Spec revision 0.6.0 indicates it needs to be set, thus set it. Note that Broadwell already locks this register. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46679/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca10146..efbaf68 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,6 +18,7 @@ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 96d08bf..bd99cee 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -24,6 +24,8 @@ /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ #define MMIO_PAVP_MSG 0x5500 +#define PCU_DDR_PTM_CTL 0x5880 + /* Some power MSRs are also represented in MCHBAR */ #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Gerrit-Change-Number: 46679 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46678 ) Change subject: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock ...................................................................... nb/intel/haswell/finalize.c: Drop obsolete SA PM lock This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect. Tested on Asrock B85M Pro4, still boots. Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46678/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index bff0344..ca10146 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,7 +18,6 @@ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); -- To view, visit https://review.coreboot.org/c/coreboot/+/46678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Gerrit-Change-Number: 46678 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/finalize.c: Use PCI register names
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46677 ) Change subject: nb/intel/haswell/finalize.c: Use PCI register names ...................................................................... nb/intel/haswell/finalize.c: Use PCI register names Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46677/1 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..bff0344 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -5,17 +5,17 @@ void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ - pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ - pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Gerrit-Change-Number: 46677 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Use get_{pmbase,gpiobase}
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45717 ) Change subject: soc/intel/broadwell: Use get_{pmbase,gpiobase} ...................................................................... soc/intel/broadwell: Use get_{pmbase,gpiobase} This is to align Broadwell and Lynx Point. Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/smihandler.c 2 files changed, 47 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45717/1 diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index c96ed18..e63a981 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -19,6 +19,12 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <security/vboot/vbnv.h> +#include <stdint.h> + +static inline uint16_t get_gpiobase(void) +{ + return GPIO_BASE_ADDRESS; +} /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -59,17 +65,17 @@ /* Enable events in PM1 control register */ void enable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt |= mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* Disable events in PM1 control register */ void disable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* @@ -79,8 +85,8 @@ /* Clear and return PM1 status register */ static u16 reset_pm1_status(void) { - u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); + u16 pm1_sts = inw(get_pmbase() + PM1_STS); + outw(pm1_sts, get_pmbase() + PM1_STS); return pm1_sts; } @@ -117,7 +123,7 @@ /* Set the PM1 register to events */ void enable_pm1(u16 events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + outw(events, get_pmbase() + PM1_EN); } /* @@ -127,8 +133,8 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); + u32 smi_sts = inl(get_pmbase() + SMI_STS); + outl(smi_sts, get_pmbase() + SMI_STS); return smi_sts; } @@ -177,17 +183,17 @@ /* Enable SMI event */ void enable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* Disable SMI event */ void disable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* @@ -200,9 +206,9 @@ u32 alt_sts, alt_en; /* Low Power variant moves this to GPIO region as dword */ - alt_sts = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); /* Only report enabled events */ return alt_sts & alt_en; @@ -235,9 +241,9 @@ { u32 alt_en; - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); alt_en |= mask; - outl(alt_en, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); } /* @@ -247,9 +253,9 @@ /* Clear TCO status and return events that are enabled and active */ static u32 reset_tco_status(void) { - u32 tcobase = ACPI_BASE_ADDRESS + 0x60; + u32 tcobase = get_pmbase() + 0x60; u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(ACPI_BASE_ADDRESS + 0x68); + u32 tco_en = inl(get_pmbase() + 0x68); /* Don't clear BOOT_STS before SECOND_TO_STS */ outl(tco_sts & ~(1 << 18), tcobase + 0x04); @@ -301,7 +307,7 @@ void enable_tco_sci(void) { /* Clear pending events */ - outl(ACPI_BASE_ADDRESS + GPE0_STS(3), TCOSCI_STS); + outl(get_pmbase() + GPE0_STS(3), TCOSCI_STS); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); @@ -314,10 +320,10 @@ /* Clear a GPE0 status and return events that are enabled and active */ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { - u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); + u32 gpe0_sts = inl(get_pmbase() + sts_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg); - outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg); + outl(gpe0_sts, get_pmbase() + sts_reg); /* Only report enabled events */ return gpe0_sts & gpe0_en; @@ -376,10 +382,12 @@ /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { - outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); - outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); - outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); - outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u16 pmbase = get_pmbase(); + + outl(set1, pmbase + GPE0_EN(GPE_31_0)); + outl(set2, pmbase + GPE0_EN(GPE_63_32)); + outl(set3, pmbase + GPE0_EN(GPE_94_64)); + outl(set4, pmbase + GPE0_EN(GPE_STD)); } /* Disable all GPE */ @@ -391,17 +399,17 @@ /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } int acpi_sci_irq(void) @@ -434,10 +442,10 @@ int platform_is_resuming(void) { - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; } /* STM Support */ diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 4a12d78..fd5d452 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -133,6 +133,7 @@ u32 reg32; u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; + u16 pmbase = get_pmbase(); /* save and recover RTC port values */ u8 tmp70, tmp72; @@ -146,7 +147,7 @@ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -225,7 +226,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -393,7 +394,7 @@ static void southbridge_smi_mc(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -436,7 +437,7 @@ static void southbridge_smi_periodic(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Gerrit-Change-Number: 45717 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46665 ) Change subject: sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null ...................................................................... sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null Use either a regular null check or `config_of` to avoid bugs. Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_xhci.c 4 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46665/1 diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 9ae6d34..dee0601 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -61,7 +61,7 @@ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - if (cfg->docking_supported) + if (cfg && cfg->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a161087..49a5226 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -141,7 +141,7 @@ static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u32 reg32 = 0; /* An array would be much nicer here, or some @@ -174,7 +174,7 @@ u32 reg32; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -282,7 +282,7 @@ /* LynxPoint LP PCH Power Management init */ static void lpt_lp_pm_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct southbridge_intel_lynxpoint_config *config = config_of(dev); u32 data; printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); @@ -636,7 +636,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 224e0f4..7af8a77 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -131,7 +131,7 @@ static void serialio_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct southbridge_intel_lynxpoint_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 60312a4..b59b433 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -328,7 +328,7 @@ /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); - } else if (config->xhci_default) { + } else if (config && config->xhci_default) { /* Route all ports to XHCI */ apm_control(APM_CNT_ROUTE_ALL_XHCI); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950 Gerrit-Change-Number: 46665 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use spaces around `|`
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46718 ) Change subject: sb/intel/lynxpoint: Use spaces around `|` ...................................................................... sb/intel/lynxpoint: Use spaces around `|` Coding style says so. Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 6 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46718/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 6a5dd40..03191d1 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -43,7 +43,7 @@ /* Enable ACPI BAR */ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a161087..5108fa5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -265,7 +265,7 @@ /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(0x3310) = reg32; reg16 = RCBA16(0x3f02); @@ -345,10 +345,10 @@ /* Set RCBA CIR28 0x3A84 based on SATA port enables */ data = 0x00001005; /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) data |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) data |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = data; @@ -489,7 +489,7 @@ * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); RCBA32_OR(0x21a8, 0x3); } diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 224e0f4..4fb84a5 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -119,7 +119,7 @@ { if (acpi_mode) { /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ - RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); + RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5)); } /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 8498a6c..f616473 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -17,7 +17,7 @@ /* Enable clock gating */ /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index a6bc5c6..f121aa8 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -119,7 +119,7 @@ static void usb_ehci_clock_gating(struct device *dev) { /* IOBP 0xE5004001[7:6] = 11b */ - pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 60312a4..a6c9eb1 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -235,7 +235,7 @@ u32 reg32; /* IOBP 0xE5004001[7:6] = 11b */ - pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6)); reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ @@ -248,7 +248,7 @@ reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ - reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); + reg32 |= (1 << 21) | (1 << 20) | (1 << 18) | (1 << 17) | (1 << 8); } /* Avoid writing upper byte as it is write-once */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a Gerrit-Change-Number: 46718 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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