coreboot-gerrit October 2020

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Change in coreboot[master]: src/drivers/ipmi: Add function to get BMC revision
by Tim Chu (Code Review) 26 Oct '20

26 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46070 ) Change subject: src/drivers/ipmi: Add function to get BMC revision ...................................................................... src/drivers/ipmi: Add function to get BMC revision Provide a way to get BMC revision. Tested=On OCP Delta Lake, function can get BMC revision well. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643 --- M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46070/1 diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 501e5dd..33ddd5f 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -33,6 +33,8 @@ * returns CB_SUCCESS on success and CB_ERR if an error occurred. */ enum cb_err ipmi_kcs_premem_init(const u16 port, const u16 device); +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision); + struct ipmi_rsp { uint8_t lun; uint8_t cmd; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3..3dec65d 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -28,6 +28,9 @@ static u8 ipmi_revision_major = 0x1; static u8 ipmi_revision_minor = 0x0; +static u8 bmc_revision_major = 0x0; +static u8 bmc_revision_minor = 0x0; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -144,6 +147,9 @@ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); @@ -272,6 +278,12 @@ } #endif +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + *ipmi_bmc_major_revision = bmc_revision_major; + *ipmi_bmc_minor_revision = bmc_revision_minor; +} + #if CONFIG(GENERATE_SMBIOS_TABLES) static int ipmi_smbios_data(struct device *dev, int *handle, unsigned long *current) -- To view, visit https://review.coreboot.org/c/coreboot/+/46070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643 Gerrit-Change-Number: 46070 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: mb/google/zork/vilboz: Enable P sensor
by Frank Wu (Code Review) 26 Oct '20

26 Oct '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45565 ) Change subject: mb/google/zork/vilboz: Enable P sensor ...................................................................... mb/google/zork/vilboz: Enable P sensor BUG=b:161759253 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 --- M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45565/1 diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 12b303a..d4bcfa5 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -10,6 +10,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { /* TP */ PAD_NC(GPIO_32), + /* P sensor INT */ + PAD_GPI(GPIO_40, PULL_NONE), /* EN_DEV_BEEP_L */ PAD_GPO(GPIO_89, HIGH), /* USI_RESET */ diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index d415de5..932805f 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -136,5 +136,12 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + device i2c 28 on end + end end end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/45565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 Gerrit-Change-Number: 45565 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: src: Remove unused <arch/io.h>
by HAOUAS Elyes (Code Review) 26 Oct '20

26 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45404 ) Change subject: src: Remove unused <arch/io.h> ...................................................................... src: Remove unused <arch/io.h> Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/ipmi/ipmi_kcs_ops_premem.c M src/include/device/pnp_ops.h M src/mainboard/51nb/x210/romstage.c M src/mainboard/asus/a88xm-e/romstage.c M src/mainboard/asus/am1i-a/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c M src/mainboard/facebook/fbg1701/ramstage.c M src/mainboard/lenovo/t440p/smihandler.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/mainboard.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/lynxpoint/early_pch.c 35 files changed, 8 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45404/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3..dd8f34c 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -8,6 +8,7 @@ * end */ +#include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pnp.h> diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c index d799be1..e1ae0dc 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops_premem.c +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <console/console.h> #include <device/pnp.h> #include <delay.h> diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 15acf36..8a6face 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -4,7 +4,6 @@ #define __DEVICE_PNP_OPS_H__ #include <stdint.h> -#include <arch/io.h> #include <device/pnp.h> #if ENV_PNP_SIMPLE_DEVICE diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 2112e25..38652b5 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -3,7 +3,6 @@ #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> -#include <arch/io.h> #include <string.h> static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c index c9ba041..1187de2 100644 --- a/src/mainboard/asus/a88xm-e/romstage.c +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> -#include <arch/io.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/smbus.h> diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index 4cfa5b1..6e71962 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <arch/io.h> #include <bootblock_common.h> #include <device/pnp_ops.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..6f23a34 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> -#include <arch/io.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 2719460..5a58f90 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -3,7 +3,6 @@ #include <cbfs.h> #include <cf9_reset.h> #include <option.h> -#include <arch/io.h> #include <cpu/x86/msr.h> #include <console/console.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 59832a47..be99573 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <console/console.h> #include <soc/ramstage.h> #include <soc/smbus.h> diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index 8cc5135..de48240 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 05a4cf2..d8e82fc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/io.h> #include <ec/acpi/ec.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index ce8d504..0ba7342 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <arch/io.h> #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f594..dea4f9b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index e5ecafe..6b9f3d0 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <stdint.h> #include <console/console.h> #include <cf9_reset.h> diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 89e7014..cccc4ca 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -7,7 +7,6 @@ #include <amdblocks/spi.h> #include <arch/exception.h> #include <arch/hlt.h> -#include <arch/io.h> #include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 46f12e7..fa8283c 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/io.h> #include <device/pci_ops.h> #include <soc/iosf.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 252a82a..3d1ea28 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <bootblock_common.h> #include <build.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 87ace88..e4b6295 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b3f4fe5..6e1a66f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -7,7 +7,6 @@ #include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 562db4e..1418d30 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a..0e31524 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e3..5bfad71 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 228e0f6..e40d248 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 6412144..8755825 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index e9b3f21..1fa3714 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cba..00850ac 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..707ae20 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 98f12a5..7ac7f5b 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <bootstate.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de..52d3e2f 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -6,7 +6,6 @@ * Chapter number: 4, 29 */ -#include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 17f801b..fb0d05c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -14,7 +14,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index bce7738..ce5e305 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,7 +26,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 59d4297..975d839 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <console/console.h> #include <device/pci_ops.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 06d7c74..a9402c7 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> -#include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <southbridge/intel/common/pmbase.h> diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac009..ace09e2 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 956d1d2..8cffe57 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Gerrit-Change-Number: 45404 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mb/google/zork: Fix get board version and get fw config issue
by EricR Lai (Code Review) 26 Oct '20

26 Oct '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46566 ) Change subject: mb/google/zork: Fix get board version and get fw config issue ...................................................................... mb/google/zork: Fix get board version and get fw config issue google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_board_version return 0 as sucess. Let's correct the logical for the false condition. BUG=None TEST=check with empty CBI value Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/dalboz/gpio.c M src/mainboard/google/zork/variants/dirinboz/gpio.c M src/mainboard/google/zork/variants/ezkinil/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c M src/mainboard/google/zork/variants/trembyle/gpio.c M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/woomax/gpio.c 9 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46566/1 diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d95ab82..9b824e1 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -57,7 +57,7 @@ return 0; } - if (google_chromeec_cbi_get_fw_config(&known_value)) { + if (google_chromeec_cbi_get_fw_config(&known_value) !=0) { printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); return -1; } @@ -95,7 +95,7 @@ if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_SCHEMATICS)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS) @@ -111,7 +111,7 @@ if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS) @@ -136,7 +136,7 @@ if (!CONFIG(VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index c8cb10f..53ae71c 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -61,7 +61,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 7600d4c..ef04341 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -47,7 +47,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 8da85b6..0a3c0fc 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -36,7 +36,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 0ec1ab23..047c3e6 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -81,7 +81,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 8da0de4..bbfde2a 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -69,7 +69,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 9931479..eb5c28e 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -60,7 +60,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version <= 2) { diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 12b303a..2ed878c 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -25,7 +25,7 @@ * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index ebbcbea..8da0742 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -60,7 +60,7 @@ uint32_t board_version; /* If board version cannot be read, assume it is board_version 0. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) !=0) board_version = 0; if (board_version == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b Gerrit-Change-Number: 46566 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

6 29

Change in coreboot[master]: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF
by David Wu (Code Review) 26 Oct '20

26 Oct '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46611 ) Change subject: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF ...................................................................... mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46611/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7486aef..b76f627 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -103,10 +103,10 @@ register "PcieClkSrcClkReq[1]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA register "SataEnable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/46611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Gerrit-Change-Number: 46611 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/volteer/var/terrador: Disable SRCCLKREQ1#
by David Wu (Code Review) 26 Oct '20

26 Oct '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46592 ) Change subject: mb/google/volteer/var/terrador: Disable SRCCLKREQ1# ...................................................................... mb/google/volteer/var/terrador: Disable SRCCLKREQ1# Disable SRCCLKREQ1# for terrador and todor. BUG=b:171278849 BRANCH=none TEST=none Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40 --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46592/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..a4112f0 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -16,6 +16,9 @@ register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "0xFF" + device domain 0 on device ref i2c0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 1ccdb87..a4112f0 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -16,6 +16,9 @@ register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "0xFF" + device domain 0 on device ref i2c0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/46592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40 Gerrit-Change-Number: 46592 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
by Sheng-Liang Pan (Code Review) 26 Oct '20

26 Oct '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46612 ) Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ...................................................................... mb/google/volteer/var/voxel: Disable SRCCLKREQ1# According to the schematic,SRCCLKREQ1# is not connected, so disable it on voxel. BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46612/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b..e8be8e3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ .tdp_pl4 = 105, }" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/46612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Gerrit-Change-Number: 46612 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: include/device/azalia_device: Fix typo
by Patrick Rudolph (Code Review) 26 Oct '20

26 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46629 ) Change subject: include/device/azalia_device: Fix typo ...................................................................... include/device/azalia_device: Fix typo Change-Id: Iee2ffb3b5170cd4c630f2b26d1eb418b239a8e23 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device/azalia_device.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46629/1 diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index d510123..58d5f72 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -54,7 +54,7 @@ STEREO_MONO_1_4, ATAPI, RCA, - OPTIONAL, + OPTICAL, OTHER_DIGITAL, OTHER_ANALOG, MULTICHANNEL_ANALOG, -- To view, visit https://review.coreboot.org/c/coreboot/+/46629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2ffb3b5170cd4c630f2b26d1eb418b239a8e23 Gerrit-Change-Number: 46629 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Karthik Ramasubramanian (Code Review) 26 Oct '20

26 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45901 ) Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 26 Oct 2020 04:48:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8192: update descriptions for dram config
by Xi Chen (Code Review) 26 Oct '20

26 Oct '20

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46616 ) Change subject: soc/mediatek/mt8192: update descriptions for dram config ...................................................................... soc/mediatek/mt8192: update descriptions for dram config MEMORY_TEST MT8192_DRAM_DVFS Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2e714c0ce588e48bbe6bd8e59c03bdb69dea01e6 --- M src/soc/mediatek/mt8192/Kconfig 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46616/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 1d1cf7b..0f42365 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -32,10 +32,15 @@ bool default n help - This options enables DRAM calibration with multiple frequencies (low, - medium and high) for DVFS feature. + This option enables DRAM calibration with multiple frequencies (low, + medium and high frequency group, total 7 freqencies) for DVFS feature. + All supported data rates are: 800, 1200, 1600, 1866, 2400, 3200, 4266. config MEMORY_TEST bool default y + help + This option enables memory basic compare test to verify the dram read + or write is as expected. + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e714c0ce588e48bbe6bd8e59c03bdb69dea01e6 Gerrit-Change-Number: 46616 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020