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Change in coreboot[master]: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM conf...
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46652 ) Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" ...................................................................... Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc. CB:45857 overrides the GPIO PM configuration if Cr50 does not support long interrupt pulse width. More recent Cr50 Firmware versions support long pulse width and hence the GPIO PM can take the default configuration. BUG=None TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of suspend/resume sequence, warm and cold reboot cycles each are successful. Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Justin TerAvest <teravest(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Evan Green <evgreen(a)chromium.org> --- D src/mainboard/google/dedede/acpi/mainboard.asl M src/mainboard/google/dedede/dsdt.asl 2 files changed, 0 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved Evan Green: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl deleted file mode 100644 index 0fa27da..0000000 --- a/src/mainboard/google/dedede/acpi/mainboard.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <intelblocks/gpio.h> -#include <soc/gpio_soc_defs.h> - -Method (PGPM, 1, Serialized) -{ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - \_SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - PGPM (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - PGPM (0) - } -} diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 1698c88..39cc25e 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -27,9 +27,6 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/jasperlake/acpi/southbridge.asl> } - - /* Mainboard hooks */ - #include "acpi/mainboard.asl" } #if CONFIG(VARIANT_HAS_CAMERA_ACPI) @@ -37,10 +34,6 @@ #include <variant/acpi/camera.asl> #endif - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/46652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Gerrit-Change-Number: 46652 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ec/google/chromeec: Update ec_commands.h
by Tim Wawrzynczak (Code Review) 26 Oct '20

26 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45937 ) Change subject: ec/google/chromeec: Update ec_commands.h ...................................................................... ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h directly from the Chromium OS EC repo at SHA 0925bb2ba. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12 --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 250 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45937/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a2..14b3ab6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -1,4 +1,7 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ /* Host communication command constants for Chrome EC */ @@ -2527,6 +2530,12 @@ */ MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2579,6 +2588,8 @@ MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, MOTIONSENSE_CHIP_MAX, }; @@ -2599,6 +2610,8 @@ /* Each sensor is up to 3-axis. */ union { int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { uint16_t reserved; uint32_t timestamp; @@ -2644,6 +2657,7 @@ MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; struct ec_motion_sense_activity { @@ -2828,6 +2842,7 @@ uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ @@ -2882,6 +2897,13 @@ uint8_t sensor_num; } online_calib_read; + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; }; } __ec_todo_packed; @@ -3033,6 +3055,10 @@ uint16_t hys_degree; } tablet_mode_threshold; + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; } __ec_todo_packed; @@ -3894,6 +3920,10 @@ /* * Unified host event programming interface - Should be used by newer versions * of BIOS/OS to program host events and masks + * + * EC returns: + * - EC_RES_INVALID_PARAM: Action or mask type is unknown. + * - EC_RES_ACCESS_DENIED: Action is prohibited for specified mask type. */ struct ec_params_host_event { @@ -4441,6 +4471,7 @@ uint32_t value; /* value to set */ } set_param; }; + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4996,6 +5027,7 @@ EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, EC_CODEC_I2S_RX_SUBCMD_COUNT, }; @@ -5109,6 +5141,33 @@ }; /*****************************************************************************/ +/* Commands for PoE PSE controller */ + +#define EC_CMD_PSE 0x00C0 + +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, +}; + +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ +}; + +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, +}; + +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ +}; + +/*****************************************************************************/ /* System commands */ /* @@ -5126,7 +5185,7 @@ EC_REBOOT_COLD = 4, /* Cold-reboot */ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5344,7 +5403,8 @@ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - uint8_t cable_speed; /* TBT_SS_* cable speed */ + /* TODO: b:158234949 Add definitions for cable speed */ + uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5727,6 +5787,8 @@ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_COUNT, }; @@ -5791,6 +5853,9 @@ #define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This * enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ struct ec_response_uptime_info { /* @@ -6053,6 +6118,7 @@ KEYBOARD_BUTTON_COUNT }; + /*****************************************************************************/ /* * "Get the Keyboard Config". An EC implementing this command is expected to be @@ -6131,6 +6197,184 @@ } __ec_align1; +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; + +/* + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. + */ +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + +/* + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. + */ +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 + +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ + struct svid_mode_info svids[0]; +} __ec_align1; + +/* USB Type-C commands for AP-controlled device policy. */ +#define EC_CMD_TYPEC_CONTROL 0x0132 + +enum typec_control_command { + TYPEC_CONTROL_COMMAND_EXIT_MODES, +}; + +struct ec_params_typec_control { + uint8_t port; + enum typec_control_command command; + /* + * This section will be interpreted based on |command|. Define a + * placeholder structure to avoid having to increase the size and bump + * the command version when adding new sub-commands. + */ + union { + uint8_t placeholder[128]; + }; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6174,6 +6418,8 @@ #define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ #define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE BIT(31) @@ -6185,6 +6431,7 @@ FP_MODE_ENROLL_IMAGE | \ FP_MODE_MATCH | \ FP_MODE_RESET_SENSOR | \ + FP_MODE_SENSOR_MAINTENANCE | \ FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12 Gerrit-Change-Number: 45937 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sconfig: Move exported device names to separate output file
by Tim Wawrzynczak (Code Review) 26 Oct '20

26 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45667 ) Change subject: sconfig: Move exported device names to separate output file ...................................................................... sconfig: Move exported device names to separate output file Both the FW_CONFIG_FIELD_* macros and exported devicetree device names were placed in static.h. Some payloads may decide they would like to consume FW_CONFIG as well, however the current status of static.h makes this impossible. To alleviate this, the exported device names are moved to a separate output file named static_devices.h. This leaves static.h with only the FW_CONFIG_FIELD* macros, making it easily consumable by payloads. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Makefile.inc M util/sconfig/main.c 2 files changed, 30 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45667/1 diff --git a/Makefile.inc b/Makefile.inc index ccc614c..b9758f0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,6 +619,9 @@ mkdir -p $(dir $(DEVICETREE_STATIC_C)) $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) +DEVICETREE_DEVICENAMES_H := $(obj)/static_devices.h +SCONFIG_OPTIONS += --output_d=$(DEVICETREE_DEVICENAMES_H) + ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) verstage-y+=$(DEVICETREE_STATIC_C) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 842c8af..a35013c 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -528,9 +528,6 @@ if (!field) return; - fprintf(fil, "\n/* firmware configuration */\n"); - fprintf(fil, "#include <fw_config.h>\n"); - while (field) { struct fw_config_option *option = field->options; uint32_t mask; @@ -1719,6 +1716,7 @@ { "chipset_devtree", 1, NULL, 'p' }, { "output_c", 1, NULL, 'c' }, { "output_h", 1, NULL, 'r' }, + { "output_d", 1, NULL, 'd' }, { "help", 1, NULL, 'h' }, { } }; @@ -1727,9 +1725,10 @@ const char *chipset_devtree = NULL; const char *outputc = NULL; const char *outputh = NULL; + const char *outputd = NULL; int opt, option_index; - while ((opt = getopt_long(argc, argv, "m:o:p:c:r:h", long_options, + while ((opt = getopt_long(argc, argv, "m:o:p:c:r:d:h", long_options, &option_index)) != EOF) { switch (opt) { case 'm': @@ -1747,13 +1746,16 @@ case 'r': outputh = strdup(optarg); break; + case 'd': + outputd = strdup(optarg); + break; case 'h': default: usage(); } } - if (!base_devtree || !outputc || !outputh) + if (!base_devtree || !outputc || !outputh || !outputd) usage(); if (chipset_devtree) { @@ -1783,14 +1785,25 @@ fclose(autogen); exit(1); } + + FILE *autodev = fopen(outputd, "w"); + if (!autodev) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputd); + perror(NULL); + fclose(autogen); + fclose(autohead); + exit(1); + } + fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); - fprintf(autohead, "#include <device/device.h>\n\n"); emit_fw_config(autohead); fprintf(autogen, "#include <device/device.h>\n"); - fprintf(autogen, "#include <device/pci.h>\n\n"); + fprintf(autogen, "#include <device/pci.h>\n"); + fprintf(autogen, "#include <fw_config.h>\n"); fprintf(autogen, "#include <static.h>\n"); + fprintf(autogen, "#include <static_devices.h>\n\n"); emit_chip_headers(autogen, chip_header.next); fprintf(autogen, "\n#define STORAGE static __unused DEVTREE_CONST\n\n"); @@ -1804,12 +1817,17 @@ walk_device_tree(autogen, autohead, &base_root_dev, pass1); /* Expose static devicenames to global namespace. */ - fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + fprintf(autodev, "#ifndef __STATIC_DEVICES_H\n"); + fprintf(autodev, "#define __STATIC_DEVICES_H\n\n"); + fprintf(autodev, "#include <device/device.h>\n\n"); + fprintf(autodev, "/* expose_device_names */\n"); + walk_device_tree(autogen, autodev, &base_root_dev, expose_device_names); fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); + fprintf(autodev, "\n#endif /* __STATIC_DEVICE_NAMES_H */\n"); fclose(autohead); fclose(autogen); + fclose(autodev); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Gerrit-Change-Number: 45667 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

7 15

Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 7
by Morgan Jang (Code Review) 26 Oct '20

26 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46068 ) Change subject: arch/x86/smbios: Update SMBIOS type 7 ...................................................................... arch/x86/smbios: Update SMBIOS type 7 Combine L1 Data cache size and L1 Instruction cache size, and multiply the cache size of L1 and L2 by the number of cores. TEST=Execute "dmidecode -t 7" to check if the cache information is correct for Deltalake platform Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 82 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46068/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index e33b70f..026849f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -476,6 +476,52 @@ return (res.eax > 0) ? 0x0c : 0x6; } +unsigned int __weak smbios_cache_error_correction_type(void) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; /* Unknown */ +} +unsigned int __weak smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_UNKNOWN; /* Unknown */ +} + +unsigned int __weak smbios_cache_conf_operation_mode(u8 level) +{ + return 3; /* Unknown */ +} + +static size_t get_number_of_caches(u32 leaf, u8 level) +{ + size_t max_logical_cpus_sharing_cache = 0; + size_t number_of_logical_cpus = 0; + size_t max_logical_cpus_per_package = 0; + struct cpuid_result res; + + /* Provide sane defaults even for CPU without CPUID */ + res.eax = res.edx = 0; + res.ebx = 0x10000; + + if (cpu_have_cpuid()) + res = cpuid(1); + + max_logical_cpus_per_package = (res.ebx >> 16) & 0xff; + + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) { + res = cpuid_ext(0xb, 1); + number_of_logical_cpus = res.ebx; + } else { + number_of_logical_cpus = max_logical_cpus_per_package; + } + + res = cpuid_ext(leaf, level); + max_logical_cpus_sharing_cache = ((res.eax >> 14) & 0xfff) + 1; + + if (max_logical_cpus_sharing_cache != max_logical_cpus_per_package) + return number_of_logical_cpus / max_logical_cpus_sharing_cache; + + return 1; +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -650,11 +696,11 @@ const enum smbios_cache_associativity associativity, const enum smbios_cache_type type, const size_t max_cache_size, - const size_t cache_size) + const size_t cache_size, + const u32 leaf) { struct smbios_type7 *t = (struct smbios_type7 *)*current; int len = sizeof(struct smbios_type7); - static unsigned int cnt = 0; char buf[8]; memset(t, 0, sizeof(struct smbios_type7)); @@ -662,13 +708,13 @@ t->handle = handle; t->length = len - 2; - snprintf(buf, sizeof(buf), "CACHE%x", cnt++); + snprintf(buf, sizeof(buf), "CACHE%x", level); t->socket_designation = smbios_add_string(t->eos, buf); t->cache_configuration = SMBIOS_CACHE_CONF_LEVEL(level) | SMBIOS_CACHE_CONF_LOCATION(0) | /* Internal */ SMBIOS_CACHE_CONF_ENABLED(1) | /* Enabled */ - SMBIOS_CACHE_CONF_OPERATION_MODE(3); /* Unknown */ + SMBIOS_CACHE_CONF_OPERATION_MODE(smbios_cache_conf_operation_mode(level)); if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) { t->max_cache_size = max_cache_size / KiB; @@ -704,11 +750,16 @@ t->installed_size2 |= SMBIOS_CACHE_SIZE2_UNIT_64KB; } + t->max_cache_size *= get_number_of_caches(leaf, level); + t->installed_size *= get_number_of_caches(leaf, level); + t->max_cache_size2 *= get_number_of_caches(leaf, level); + t->installed_size2 *= get_number_of_caches(leaf, level); + t->associativity = associativity; t->supported_sram_type = sram_type; t->current_sram_type = sram_type; t->cache_speed = 0; /* Unknown */ - t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->error_correction_type = smbios_cache_error_correction_type(); t->system_cache_type = type; len = t->length + smbios_string_table_len(t->eos); @@ -767,6 +818,7 @@ unsigned int cnt = 0; int len = 0; u32 leaf; + size_t cache0_size = 0; if (!cpu_have_cpuid()) return len; @@ -803,7 +855,8 @@ const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; - const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; + size_t cache_size = assoc * partitions * cache_line_size * + number_of_sets; if (!cache_type) /* No more caches in the system */ @@ -829,11 +882,21 @@ else associativity = smbios_cache_associativity(assoc); + if (level == 1 && type == SMBIOS_CACHE_TYPE_DATA) { + cache0_size = cache_size; + continue; + } + + if (level == 1 && type == SMBIOS_CACHE_TYPE_INSTRUCTION) { + cache_size += cache0_size; + type = SMBIOS_CACHE_TYPE_UNIFIED; + } + const int h = (*handle)++; update_max(len, *max_struct_size, smbios_write_type7(current, h, - level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, - type, cache_size, cache_size)); + level, smbios_cache_sram_type(), associativity, + type, cache_size, cache_size, leaf)); if (type4) { switch (level) { diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..216c8f6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -59,6 +59,10 @@ struct cpuid_result; unsigned int smbios_processor_family(struct cpuid_result res); +unsigned int smbios_cache_error_correction_type(void); +unsigned int smbios_cache_sram_type(void); +unsigned int smbios_cache_conf_operation_mode(u8 level); + /* Used by mainboard to add port information of type 8 */ struct port_information; int smbios_write_type8(unsigned long *current, int *handle, @@ -499,6 +503,13 @@ #define SMBIOS_CACHE_SIZE2_UNIT_64KB (1UL << 31) #define SMBIOS_CACHE_SIZE2_MASK 0x7fffffff +/* define for cache operation mode */ + +#define SMBIOS_CACHE_OP_MODE_WRITE_THROUGH 0 +#define SMBIOS_CACHE_OP_MODE_WRITE_BACK 1 +#define SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS 2 +#define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 + struct smbios_type7 { u8 type; u8 length; -- To view, visit https://review.coreboot.org/c/coreboot/+/46068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04 Gerrit-Change-Number: 46068 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

7 41

Change in coreboot[master]: sb/amd/*/*/pci_devs.h: Reduce the difference
by HAOUAS Elyes (Code Review) 26 Oct '20

26 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45894 ) Change subject: sb/amd/*/*/pci_devs.h: Reduce the difference ...................................................................... sb/amd/*/*/pci_devs.h: Reduce the difference Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/cimx/sb800/pci_devs.h M src/southbridge/amd/pi/hudson/pci_devs.h 3 files changed, 169 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/45894/1 diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 94417aa..d67395c 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -5,103 +5,103 @@ #include <device/pci_def.h> -#define BUS0 0 +#define BUS0 0 /* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7814 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) /* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7800 -#define AHCI_DEVID_MS 0x7801 -#define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7800 +#define AHCI_DEVID_MS 0x7801 +#define AHCI_DEVID_AMD 0x7804 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -#define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x7807 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -#define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x16 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x7808 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* SMBUS */ -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x780B +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* IDE */ #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -# define IDE_DEVID 0x780C -# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +#define IDE_DEVID 0x780C +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif /* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -#define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x780D +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV +#define LPC_FUNC 3 +#define LPC_DEVID 0x780E +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -# define SB_PCI_PORT_DEVID 0x780F -# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +#define SB_PCI_PORT_DEVID 0x780F +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ -#define SD_DEV 0x14 -#define SD_FUNC 7 -#define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7806 +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) /* PCIe Ports */ #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -#define SB_PCIE_PORT1_DEVID 0x7820 -#define SB_PCIE_PORT2_DEVID 0x7821 -#define SB_PCIE_PORT3_DEVID 0x7822 -#define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif #endif /* _AGESA_HUDSON_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h index 8f730e3..91825ba 100644 --- a/src/southbridge/amd/cimx/sb800/pci_devs.h +++ b/src/southbridge/amd/cimx/sb800/pci_devs.h @@ -5,86 +5,88 @@ #include <device/pci_def.h> -#define BUS0 0 +#define BUS0 0 /* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -# define SATA_IDE_DEVID 0x4390 -# define AHCI_DEVID 0x4391 -# define RAID_DEVID 0x4392 -# define RAID5_DEVID 0x4393 -# define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x4390 +#define AHCI_DEVID 0x4391 +#define RAID_DEVID 0x4392 +#define RAID5_DEVID 0x4393 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -# define OHCI_DEVID 0x4397 -# define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -# define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -# define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -# define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x4397 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -# define EHCI_DEVID 0x4396 -# define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -# define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -# define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) - -/* IDE */ -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -# define IDE_DEVID 0x439C -# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -# define HDA_DEVID 0x4383 -# define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) - -/* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -# define SB_PCI_PORT_DEVID 0x4384 -# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) - -/* PCIe Ports */ -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -# define SB_PCIE_PORT1_DEVID 0x43A0 -# define SB_PCIE_PORT2_DEVID 0x43A1 -# define SB_PCIE_PORT3_DEVID 0x43A2 -# define SB_PCIE_PORT4_DEVID 0x43A3 -# define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -# define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -# define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -# define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x16 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x4396 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* Fusion Controller Hub */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -# define LPC_DEVID 0x439D -# define SMBUS_DEVID 0x4385 -# define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x4385 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) + +/* IDE */ +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +#define IDE_DEVID 0x439C +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) + +/* HD Audio */ +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x4383 +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV +#define LPC_FUNC 3 +#define LPC_DEVID 0x439D +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) + +/* PCI Ports */ +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +#define SB_PCI_PORT_DEVID 0x4384 +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) + +/* PCIe Ports */ +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x43A0 +#define SB_PCIE_PORT2_DEVID 0x43A1 +#define SB_PCIE_PORT3_DEVID 0x43A2 +#define SB_PCIE_PORT4_DEVID 0x43A3 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif /* _CIMX_SB800_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 7c29380..5dece33 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -3,18 +3,20 @@ #ifndef _PI_HUDSON_PCI_DEVS_H_ #define _PI_HUDSON_PCI_DEVS_H_ +#include <device/pci_def.h> + #define BUS0 0 /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 #define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define XHCI2_DEV 0x10 #define XHCI2_FUNC 1 #define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -22,7 +24,7 @@ #define SATA_IDE_DEVID 0x7800 #define AHCI_DEVID_MS 0x7801 #define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ #define OHCI1_DEV 0x12 @@ -34,10 +36,10 @@ #define OHCI4_DEV 0x14 #define OHCI4_FUNC 5 #define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ #define EHCI1_DEV 0x12 @@ -47,48 +49,48 @@ #define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 #define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 #define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* IDE */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define IDE_DEV 0x14 #define IDE_FUNC 1 #define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 #define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_DEV PCU_DEV #define LPC_FUNC 3 #define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ #define SB_PCI_PORT_DEV 0x14 #define SB_PCI_PORT_FUNC 4 #define SB_PCI_PORT_DEVID 0x780F -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 #define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) /* PCIe Ports */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) @@ -101,10 +103,10 @@ #define SB_PCIE_PORT2_DEVID 0x7821 #define SB_PCIE_PORT3_DEVID 0x7822 #define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif #endif /* _PI_HUDSON_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68 Gerrit-Change-Number: 45894 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/amd/*/*/smbus.h: Make 'smbus.h' uniform
by HAOUAS Elyes (Code Review) 26 Oct '20

26 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45892 ) Change subject: sb/amd/*/*/smbus.h: Make 'smbus.h' uniform ...................................................................... sb/amd/*/*/smbus.h: Make 'smbus.h' uniform Reformat 'smbus.h' files and add missing <stdint.h>. Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/cimx/sb800/smbus.h M src/southbridge/amd/pi/hudson/smbus.h 3 files changed, 44 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45892/1 diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 6381d97..96ff574 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -5,29 +5,29 @@ #include <stdint.h> -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 0a1b279..8db8d62 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -3,33 +3,33 @@ #ifndef _SB800_SMBUS_H_ #define _SB800_SMBUS_H_ +#include <stdint.h> + #define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc -/*//SB00.H -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 -*/ +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index 2398910..96ff574 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -26,8 +26,8 @@ #define RC_INDXC 1 #define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. -- To view, visit https://review.coreboot.org/c/coreboot/+/45892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664 Gerrit-Change-Number: 45892 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL
by Johnny Lin (Code Review) 26 Oct '20

26 Oct '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45326 ) Change subject: mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL ...................................................................... mb/ocp/deltalake: Select CONSOLE_VPD_OVERRIDE_LOGLEVEL And set CONSOLE_VPD_DEFAULT_LOGLEVEL to 4 if the VPD variable is not found. Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45326/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b229c94..9fab7de 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CONSOLE_VPD_OVERRIDE_LOGLEVEL select FSP_CAR select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 @@ -51,4 +52,8 @@ bool default y +config CONSOLE_VPD_DEFAULT_LOGLEVEL + int + default 4 + endif # BOARD_OCP_DELTALAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/45326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Gerrit-Change-Number: 45326 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46463 ) Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers ...................................................................... cpu/intel/common: implement the two missing CPPC v2 autonomous registers This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Matt Delco <delco(a)chromium.org> --- M src/cpu/intel/common/common_init.c 1 file changed, 16 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Matt Delco: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index d0b66d4..3ea8f36 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -239,11 +239,23 @@ if (version >= 2) { /* Autonomous Selection Enable is populated below */ - /* Autonomous Activity Window Register */ - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + msr.addrl = IA32_HWP_REQUEST; - /* Energy Performance Preference Register */ - config->regs[CPPC_PERF_PREF] = unsupported; + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + msr.bit_width = 10; + msr.bit_offset = 32; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; /* Reference Performance */ config->regs[CPPC_REF_PERF] = unsupported; -- To view, visit https://review.coreboot.org/c/coreboot/+/46463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Gerrit-Change-Number: 46463 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... soc/intel/icl: enable common CPU code Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/icelake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5736749..3b3d479 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -11,6 +11,8 @@ select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select SET_IA32_FC_LOCK_BIT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 51 files changed, 2 insertions(+), 116 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Frans Hendriks: Looks good to me, approved diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 294ae44..561bd6f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -28,9 +28,6 @@ register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d6f29a2..57acd33 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -18,9 +18,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 8f256ad..e8827bf 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index bb11d06..15ab7ef 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -29,9 +29,6 @@ # "Intel SpeedStep Technology" register "eist_enable" = "1" - # "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11d..4713589 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -136,9 +136,6 @@ register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 775c548..bbb63bc 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -134,9 +134,6 @@ register "gpio_pm[3]" = "0" register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aa6af87..de3b5ca 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a2550bb..519e53b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -227,7 +227,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 9c11e80..703ef5b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -305,7 +305,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_psyspl2 = 90, .psys_pmax = 120, diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 12312e9..2dfb71f 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -30,9 +30,6 @@ register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 10ad029..cdd83df 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -29,8 +29,6 @@ register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" # Enable DPTF diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 9f9d951..3797fb0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -59,7 +59,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0dc9131..0b3d6c0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -246,7 +246,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 167bd03..d408f9e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -266,8 +266,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" - register "tcc_offset" = "3" # TCC of 97C register "power_limits_config" = "{ .psys_pmax = 101, diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ed21492..b7d171b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -268,7 +268,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0a29601..ab1588a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -54,8 +54,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - # Set speed_shift_enable to 1 to enable P-States, and 0 to disable - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 591e0fb..2334a17 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -225,7 +225,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 18W for AML-Y register "power_limits_config" = "{ .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b3570d7..c698755 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -247,7 +247,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b1d9a36..3ff9b30 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -29,7 +29,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e1ee6c9..17d0127 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -32,7 +32,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b76f627..2a62505 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -230,9 +230,6 @@ register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 818f32f..7305501 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -13,8 +13,6 @@ register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - # Enable Speed Shift Technology/HWP support - register "speed_shift_enable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e100598..1110bc1 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -60,9 +60,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bf7aa1e..4202314 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -57,9 +57,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 0b40a5c..12b1c47 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -43,9 +43,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 49303da..1215628 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -152,9 +152,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index a1c32c9..e8c6e8f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -152,9 +152,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b9aec37..61a5e70 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -122,9 +122,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 8de089d..e17c8b7 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 3afff45..07afb7b 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -17,9 +17,6 @@ register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index a25cb8c..5c64326 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -14,9 +14,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 09ab258..de93c99 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,9 +115,6 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 25c2293..4078894 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -119,9 +119,6 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 357f8fa..ef1f0d4 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -2,8 +2,6 @@ chip soc/intel/skylake - register "speed_shift_enable" = "1" - register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d47eca8..911690f 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -30,9 +30,6 @@ register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 071fc5f..04e6774 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -126,8 +126,6 @@ # Thermal register "tcc_offset" = "6" # TCC of 94C - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" # Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 2a4b1e9..e6e748a 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,8 +17,6 @@ register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" register "eist_enable" = "1" # Disable DPTF diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 23c5712..2c73280 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -37,9 +37,6 @@ register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index 497a4cc..2050332 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -24,9 +24,6 @@ .tdp_pl2_override = 28, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index edf1333..4f8ceb6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,9 +19,6 @@ register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 505e9a4..cca8838 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -4,7 +4,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1" register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 5a2fc01..3c9d968 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -4,7 +4,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1" register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index dd0e520..e7b26dc 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,9 +3,6 @@ register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 277570e..84c0312 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index aaf03f5..428fd4d 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -185,8 +185,6 @@ uint8_t HeciEnabled; /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 69a2cf2..7f428a2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -261,8 +261,6 @@ /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5037147..26d0f0d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -149,8 +149,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 386e775..e1b697e 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -169,8 +169,7 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; + /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 4410de9..5e90530 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -149,8 +149,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2584d5d..41482f1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -461,8 +461,7 @@ */ u8 HeciEnabled; u8 PmTimerDisabled; - /* Intel Speed Shift Technology */ - u8 speed_shift_enable; + /* * Enable VR specific mailbox command * 000b - Don't Send any VR command diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb6cda0..f752b5f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -271,9 +271,6 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2020