coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/asurada: change EC SPI to 3M
by Yidi Lin (Code Review) 26 Oct '20

26 Oct '20

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46394 to review the following change. Change subject: mb/google/asurada: change EC SPI to 3M ...................................................................... mb/google/asurada: change EC SPI to 3M To prevent timeout on long EC packet, we should increase EC SPI speed to the same value that kernel is using (3M). BUG=b:161509047 TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d --- M src/mainboard/google/asurada/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/1 diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 04e8898..647555a 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -7,7 +7,7 @@ void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); setup_chromeos_gpios(); gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); -- To view, visit https://review.coreboot.org/c/coreboot/+/46394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d Gerrit-Change-Number: 46394 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 26 Oct '20

26 Oct '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 53: 105 > Is this supposed to be 100 as shared in the report on the bug? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 26 Oct 2020 02:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 26 Oct '20

26 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#5). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/acpi: Add pch.asl
by Marc Jones (Code Review) 26 Oct '20

26 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45836 ) Change subject: soc/intel/xeon_sp/acpi: Add pch.asl ...................................................................... soc/intel/xeon_sp/acpi: Add pch.asl Add ASL for the PCH. Initially, this only contains soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL may be added in the future. Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- A src/soc/intel/xeon_sp/acpi/pch.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45836/1 diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/pch.asl new file mode 100644 index 0000000..98a5fdd --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pch.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file should be included in the proper platform ACPI \_SB PCI scope */ + +/* LPC 0:1f.0 */ +#include <soc/intel/common/block/acpi/acpi/lpc.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Gerrit-Change-Number: 45836 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/broadwell: Drop chip.c file
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46698 ) Change subject: soc/intel/broadwell: Drop chip.c file ...................................................................... soc/intel/broadwell: Drop chip.c file Prepare to break down Broadwell into CPU, northbridge and southbridge. Change-Id: Ic844cc3bbff760fa0eed9d81208bbeef39577e9d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/systemagent.c 3 files changed, 38 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46698/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 786fe2a..e24b949 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -18,7 +18,6 @@ ramstage-y += acpi.c ramstage-y += adsp.c -ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c deleted file mode 100644 index 9358c78..0000000 --- a/src/soc/intel/broadwell/chip.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> - -static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = &broadwell_init_cpus, -}; - -static void broadwell_enable(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } - } -} - -struct chip_operations soc_intel_broadwell_ops = { - CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, - .init = &broadwell_init_pre_device, -}; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 0837e0c..4b4848b 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -10,6 +10,7 @@ #include <device/pci_ids.h> #include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -451,3 +452,40 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = systemagent_ids }; + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = &broadwell_init_cpus, +}; + +static void broadwell_enable(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + broadwell_pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_broadwell_ops = { + CHIP_NAME("Intel Broadwell") + .enable_dev = &broadwell_enable, + .init = &broadwell_init_pre_device, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic844cc3bbff760fa0eed9d81208bbeef39577e9d Gerrit-Change-Number: 46698 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: soc/intel/broadwell: Drop `broadwell_pci_ops`
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46697 ) Change subject: soc/intel/broadwell: Drop `broadwell_pci_ops` ...................................................................... soc/intel/broadwell: Drop `broadwell_pci_ops` This is essentially a duplicate of `pci_dev_ops_pci`. Change-Id: I06a21ebd759c35910cd753d3079ea7902868e89d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/xhci.c 13 files changed, 11 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46697/1 diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 15858e1..220ad6f 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -128,7 +128,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = adsp_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 16afcce..9358c78 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -43,7 +43,3 @@ .enable_dev = &broadwell_enable, .init = &broadwell_init_pre_device, }; - -struct pci_operations broadwell_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem -}; diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 8ccd278..c77f5c4 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -590,7 +590,7 @@ .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &igd_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 1640825..04390d1 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -139,7 +139,7 @@ .enable_resources = &pci_dev_enable_resources, .init = &hda_init, .enable = &hda_enable, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 18a23e1..0b6ef0d 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -16,6 +16,4 @@ static inline void broadwell_run_reference_code(void) { } #endif -extern struct pci_operations broadwell_pci_ops; - #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index ccd372c..dd4e15c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -652,7 +652,7 @@ .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, .scan_bus = &scan_static_bus, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 7449902..80ffe2b 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -1041,7 +1041,7 @@ .enable = &intel_me_enable, .init = &intel_me_init, .final = &intel_me_finalize, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index a39c496..6d96eb3 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -95,7 +95,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index b1d953e..c9168325 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -270,7 +270,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index dbe194a..766f5dd 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -273,7 +273,7 @@ .set_resources = &serialio_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &serialio_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 31715c7..0bc2c2b 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -79,7 +79,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 91816be..0837e0c 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -435,7 +435,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = systemagent_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short systemagent_ids[] = { diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 526781d..baaf5ba 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -201,7 +201,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, .init = xhci_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06a21ebd759c35910cd753d3079ea7902868e89d Gerrit-Change-Number: 46697 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/gma.c: Drop unused ChromeOS include
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46693 ) Change subject: nb/intel/haswell/gma.c: Drop unused ChromeOS include ...................................................................... nb/intel/haswell/gma.c: Drop unused ChromeOS include Change-Id: I598fe743354ea429d6821b95be7d209a9fcf9f0c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46693/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 9627945..66c8d2d 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -21,10 +21,6 @@ #include "chip.h" #include "haswell.h" -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif - struct gt_reg { u32 reg; u32 andmask; -- To view, visit https://review.coreboot.org/c/coreboot/+/46693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598fe743354ea429d6821b95be7d209a9fcf9f0c Gerrit-Change-Number: 46693 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/lippert/frontrunner-af: frontrunner-af: Add blank line in code
by Paul Menzel (Code Review) 25 Oct '20

25 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46716 ) Change subject: mb/lippert/frontrunner-af: frontrunner-af: Add blank line in code ...................................................................... mb/lippert/frontrunner-af: frontrunner-af: Add blank line in code Adding the blank line, reduces the differences with the variant toucan-af. Change-Id: I58bfc99109a2df2eab54a562dc13e7bd946890d9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46716/1 diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c index 71d0f41..e32e125 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c @@ -79,6 +79,7 @@ iomux_write8(190, 1); iomux_write8(191, 1); iomux_write8(192, 1); + /* just in case anyone cares */ if (!fch_gpio_state(197)) printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/46716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58bfc99109a2df2eab54a562dc13e7bd946890d9 Gerrit-Change-Number: 46716 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/gma.c: Drop unused `set_translation_table` function
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46692 ) Change subject: nb/intel/haswell/gma.c: Drop unused `set_translation_table` function ...................................................................... nb/intel/haswell/gma.c: Drop unused `set_translation_table` function Change-Id: I6c65a5a74a83b8da299245fd6f4a7ae7c1ed30c3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46692/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 989d100..9627945 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -120,47 +120,6 @@ return new_vendev; } -/** FIXME: Seems to be outdated. */ -/* - * GTT is the Global Translation Table for the graphics pipeline. It is used to translate - * graphics addresses to physical memory addresses. As in the CPU, GTTs map 4K pages. - * - * The setgtt function adds a further bit of flexibility: it allows you to set a range (the - * first two parameters) to point to a physical address (third parameter); the physical address - * is incremented by a count (fourth parameter) for each GTT in the range. - * - * Why do it this way? For ultrafast startup, we can point all the GTT entries to point to one - * page, and set that page to 0s: - * - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * - * this takes about 2 ms, and is a win because zeroing the page takes up to 200 ms. - * - * This call sets the GTT to point to a linear range of pages starting at physbase. - */ - -#define GTT_PTE_BASE (2 << 20) - -void set_translation_table(int start, int end, u64 base, int inc) -{ - int i; - - for (i = start; i < end; i++){ - u64 physical_address = base + i * inc; - - /* swizzle the 32:39 bits to 4:11 */ - u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1; - - /* - * Note: we've confirmed by checking the values that MRC does no useful - * setup before we run this. - */ - gtt_write(GTT_PTE_BASE + i * 4, word); - gtt_read(GTT_PTE_BASE + i * 4); - } -} - static struct resource *gtt_res = NULL; u32 gtt_read(u32 reg) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b160f83..edca2b6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -90,7 +90,6 @@ void haswell_early_initialization(void); void haswell_late_initialization(void); -void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); void report_platform_info(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c65a5a74a83b8da299245fd6f4a7ae7c1ed30c3 Gerrit-Change-Number: 46692 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lippert/frontrunner-af: frontrunner-af: Remove unused header include
by Paul Menzel (Code Review) 25 Oct '20

25 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46715 ) Change subject: mb/lippert/frontrunner-af: frontrunner-af: Remove unused header include ...................................................................... mb/lippert/frontrunner-af: frontrunner-af: Remove unused header include Change-Id: If1d4128055a0fd50d109b4aa04c7d0c8ebb2f6c5 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46715/1 diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c index 070da4e..4bb4c10 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1d4128055a0fd50d109b4aa04c7d0c8ebb2f6c5 Gerrit-Change-Number: 46715 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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