coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... soc/intel/skl: replace conditional on dt option reading CPUID for CPPC Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/acpi.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 275e77d..637092b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -35,6 +35,8 @@ #include "chip.h" +#define CPUID_6_EAX_ISST (1 << 7) + /* * List of suported C-states in this processor. */ @@ -379,7 +381,7 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config->speed_shift_enable) { + if (cpuid_eax(6) & CPUID_6_EAX_ISST) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); @@ -405,7 +407,7 @@ cores_per_package); } - if (config->speed_shift_enable) + if (cpuid_eax(6) & CPUID_6_EAX_ISST) acpigen_write_CPPC_method(); acpigen_pop_len(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46460 ) Change subject: soc/intel: drop unneeded ISST configuration code ...................................................................... soc/intel: drop unneeded ISST configuration code The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 7 files changed, 0 insertions(+), 196 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 9b7cc3e..39a4265 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -31,31 +31,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -122,9 +97,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index b6b921a..20da942 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -27,31 +27,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -158,9 +133,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index c51f3fa..720a295 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -25,31 +25,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -116,9 +91,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index b739d74..ea2b357 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -25,31 +25,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -152,9 +127,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 6f071c3..312fc7d 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -25,31 +25,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -116,9 +91,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index fcec0cef..1682503 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,31 +27,6 @@ #include "chip.h" -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { config_t *conf = config_of_soc(); @@ -163,9 +138,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index e13712d..d7234e7 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -31,31 +31,6 @@ fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -122,9 +97,6 @@ /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Gerrit-Change-Number: 46460 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/intelp2m: Fix typos
by Patrick Georgi (Code Review) 26 Oct '20

26 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45007 ) Change subject: util/intelp2m: Fix typos ...................................................................... util/intelp2m: Fix typos Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/intelp2m/description.md M util/intelp2m/fields/cb/cb.go M util/intelp2m/fields/fsp/fsp.go M util/intelp2m/main.go 4 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index 9ca56b9..1aaee40 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -23,9 +23,9 @@ 0 - inteltool.log (default) 1 - gpio.h 2 - your template -(shell)$ ./intelp2m -t 1 -file coreboot/src/mainboard/youboard/gpio.h +(shell)$ ./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h ``` -You can also add add a template to 'parser/template.go' for your file type with +You can also add a template to 'parser/template.go' for your file type with the configuration of the pads. platform type is set using the -p option (Sunrise by default): @@ -35,7 +35,7 @@ snr - Sunrise PCH with Skylake/Kaby Lake CPU lbg - Lewisburg PCH with Xeon SP CPU apl - Apollo Lake SoC - cnl - CannonLake-LP or Whiskeylake/Coffelake/Cometlake-U SoC + cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC (default "snr") (shell)$ ./intelp2m -p <platform> -file path/to/inteltool.log diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go index 2a87cda..3bda62e 100644 --- a/util/intelp2m/fields/cb/cb.go +++ b/util/intelp2m/fields/cb/cb.go @@ -19,11 +19,11 @@ } // generate - wrapper for generating bitfield macros string -// fileds : field structure -func generate(fileds ...*field) { +// fields : field structure +func generate(fields ...*field) { macro := common.GetMacro() var allhidden bool = true - for _, field := range fileds { + for _, field := range fields { if field.unhide { allhidden = false macro.Or() diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/fields/fsp/fsp.go index fa26b5a..360333a 100644 --- a/util/intelp2m/fields/fsp/fsp.go +++ b/util/intelp2m/fields/fsp/fsp.go @@ -15,10 +15,10 @@ } // generate - wrapper for generating bitfield macros string -// fileds : field structure -func generate(fileds ...*field) { +// fields : field structure +func generate(fields ...*field) { macro := common.GetMacro() - for _, field := range fileds { + for _, field := range fields { if field.override != nil { // override if necessary field.override(field.configmap, field.value) diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index a7bbc91..511f54d 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -67,9 +67,9 @@ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ - "\tcnl - CannonLake-LP or Whiskeylake/Coffelake/Cometlake-U SoC\n") + "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n") - filedstyle := flag.String("fld", "none", "set fileds macros style:\n"+ + fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+ "\tcb - use coreboot style for bit fields macros\n"+ "\tfsp - use fsp style\n"+ "\traw - do not convert, print as is\n") @@ -106,8 +106,8 @@ os.Exit(1) } - if config.FldStyleSet(*filedstyle) != 0 { - fmt.Printf("Error! Unknown bit fields style option -%s!\n", *filedstyle) + if config.FldStyleSet(*fieldstyle) != 0 { + fmt.Printf("Error! Unknown bit fields style option -%s!\n", *fieldstyle) os.Exit(1) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697 Gerrit-Change-Number: 45007 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console/init: Drop CONSOLE_LEVEL_CONST
by Nico Huber (Code Review) 26 Oct '20

26 Oct '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45765 to review the following change. Change subject: console/init: Drop CONSOLE_LEVEL_CONST ...................................................................... console/init: Drop CONSOLE_LEVEL_CONST We limited the configurability of the debug level to stages that have a `.data` section. This is not really a requirement, because a `.bss` section should suffice and we always have that now. Making the debug level always configurable, adds an early call to get_option(). But that shouldn't hurt: The value is cached locally. Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/init.c 1 file changed, 2 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45765/1 diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..9776e2a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -8,40 +8,24 @@ #include <option.h> #include <version.h> -/* Mutable console log level only allowed when RAM comes online. */ -#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION - static int console_inited; -static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +static int console_loglevel; static inline int get_log_level(void) { if (console_inited == 0) return -1; - if (CONSOLE_LEVEL_CONST) - return get_console_loglevel(); return console_loglevel; } -static inline void set_log_level(int new_level) -{ - if (CONSOLE_LEVEL_CONST) - return; - - console_loglevel = new_level; -} - static void init_log_level(void) { int debug_level = get_console_loglevel(); - if (CONSOLE_LEVEL_CONST) - return; - get_option(&debug_level, "debug_level"); - set_log_level(debug_level); + console_loglevel = debug_level; } int console_log_level(int msg_level) -- To view, visit https://review.coreboot.org/c/coreboot/+/45765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Gerrit-Change-Number: 45765 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR
by Sheng-Liang Pan (Code Review) 26 Oct '20

26 Oct '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46618 ) Change subject: mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR ...................................................................... mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR enable GPP_D17 for camera power. BUG=b:169170677 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218 --- M src/mainboard/google/volteer/variants/voxel/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46618/1 diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index b5d070b..6e5fc0b 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -114,7 +114,7 @@ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPO(GPP_D17, 1, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), -- To view, visit https://review.coreboot.org/c/coreboot/+/46618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218 Gerrit-Change-Number: 46618 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tspi/crtm: Add line break to debug messages
by Frans Hendriks (Code Review) 26 Oct '20

26 Oct '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46659 ) Change subject: security/tpm/tspi/crtm: Add line break to debug messages ...................................................................... security/tpm/tspi/crtm: Add line break to debug messages Add line break at debug messages. Tested on Facebook FBG1701 Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tspi/crtm.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46659/1 diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index d9c62e1..eb07442 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -112,10 +112,10 @@ if (!tcpa_log_available()) { if (tspi_init_crtm() != VB2_SUCCESS) { printk(BIOS_WARNING, - "Initializing CRTM failed!"); + "Initializing CRTM failed!\n"); return 0; } - printk(BIOS_DEBUG, "CRTM initialized."); + printk(BIOS_DEBUG, "CRTM initialized.\n"); } cbfsf_file_type(fh, &cbfs_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/46659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e Gerrit-Change-Number: 46659 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/var/fleex: Add goodix touch pad support
by EricR Lai (Code Review) 26 Oct '20

26 Oct '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46614 ) Change subject: mb/google/octopus/var/fleex: Add goodix touch pad support ...................................................................... mb/google/octopus/var/fleex: Add goodix touch pad support Add goodix touch pad as below: HWID: GXTP7288 CID:PNP0C50 I2C address:0x2C I2C speed:400Khz HID Descriptor Address:0x20 BUG=b:171351666 BRANCH=octopus TEST=build image and verify goodix touch pad working. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29 --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46614/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 0b81752..679b101 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -128,6 +128,15 @@ register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end # - I2C 6 device pci 17.3 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/46614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29 Gerrit-Change-Number: 46614 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smbus: Add define for I2C_EN
by Patrick Rudolph (Code Review) 26 Oct '20

26 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46563 ) Change subject: soc/intel/common/block/smbus: Add define for I2C_EN ...................................................................... soc/intel/common/block/smbus: Add define for I2C_EN Change-Id: Iecccc363f492985555019f2390bd53472a000ba9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/smbus/smbuslib.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46563/1 diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 05cecf3..4548b75 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -10,6 +10,8 @@ /* PCI Configuration Space : SMBus */ #define HOSTC 0x40 #define HST_EN (1 << 0) +#define I2C_EN (1 << 2) + /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecccc363f492985555019f2390bd53472a000ba9 Gerrit-Change-Number: 46563 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
by Patrick Rudolph (Code Review) 26 Oct '20

26 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46562 ) Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ...................................................................... soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID Tis is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration. Tested on Prodrive Hermes. Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46562/1 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ae9f650..f97defb 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -76,6 +76,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_SMBUS, + PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER, -- To view, visit https://review.coreboot.org/c/coreboot/+/46562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Gerrit-Change-Number: 46562 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Use BMC version to represent ec version
by Tim Chu (Code Review) 26 Oct '20

26 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46071 ) Change subject: mb/ocp/deltalake: Use BMC version to represent ec version ...................................................................... mb/ocp/deltalake: Use BMC version to represent ec version In deltalake, there's no embedded controller and BMC version is used to represent ec version. TEST=Build with CB:45138 and CB:46070 Execute "dmidecode -t 0" to check if the firmware version is correct Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46071/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..625634c 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -26,6 +26,19 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; +/* + * Update SMBIOS type 0 ec version. + * In deltalake, BMC version is used to represent ec version. + */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + uint8_t bmc_major_revision, bmc_minor_revision; + + ipmi_bmc_version(&bmc_major_revision, &bmc_minor_revision); + *ec_major_revision = bmc_major_revision & 0x7f; /* bit[6:0] Major Firmware Revision */ + *ec_minor_revision = ((bmc_minor_revision / 16) * 10) + (bmc_minor_revision % 16); +} + /* Override SMBIOS 2 Location In Chassis from BMC */ const char *smbios_mainboard_location_in_chassis(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e Gerrit-Change-Number: 46071 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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