coreboot-gerrit October 2020

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Change in coreboot[master]: mb/lippert/frontrunner-af: frontrunner-af: Add board URL
by Paul Menzel (Code Review) 25 Oct '20

25 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46714 ) Change subject: mb/lippert/frontrunner-af: frontrunner-af: Add board URL ...................................................................... mb/lippert/frontrunner-af: frontrunner-af: Add board URL Change-Id: If58d87296ed6fb176d4bc42ba6f6f39ca069adfd Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46714/1 diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt index 4a443cd..00f3dcb 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt @@ -1,4 +1,5 @@ Category: half +Board URL: https://www.adlinktech.com/Products/PC104SBCs/PC_104_Plus_SBCs/CM2-GF ROM package: SOIC8 ROM protocol: SPI ROM socketed: n -- To view, visit https://review.coreboot.org/c/coreboot/+/46714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If58d87296ed6fb176d4bc42ba6f6f39ca069adfd Gerrit-Change-Number: 46714 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/broadwell/chip.h: Drop unused intelblocks include
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46699 ) Change subject: soc/intel/broadwell/chip.h: Drop unused intelblocks include ...................................................................... soc/intel/broadwell/chip.h: Drop unused intelblocks include Change-Id: I499df8c282e168f9b883c2377d6b2692a355f92a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/chip.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46699/1 diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index ae43353..45d512a 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,7 +4,6 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include <drivers/intel/gma/i915.h> -#include <intelblocks/cfg.h> #include <stdint.h> struct soc_intel_broadwell_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/46699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I499df8c282e168f9b883c2377d6b2692a355f92a Gerrit-Change-Number: 46699 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/alderlake/romstage: Skip GPIO configuration from FSP
by Subrata Banik (Code Review) 25 Oct '20

25 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46696 ) Change subject: soc/intel/alderlake/romstage: Skip GPIO configuration from FSP ...................................................................... soc/intel/alderlake/romstage: Skip GPIO configuration from FSP Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases TEST=Able to build and boot ADLRVP to OS. Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46696/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 38c1a1b..868d75e 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -157,6 +157,9 @@ m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/46696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Gerrit-Change-Number: 46696 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432
by Subrata Banik (Code Review) 25 Oct '20

25 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46695 ) Change subject: vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432 ...................................................................... vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432 List of changes: 1. FSP-M Header: - Add new UPD GpioOverride - Change help text for PlatformDebugConsent UPD - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust Reservedxx UPD Offset Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 291 insertions(+), 272 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46695/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 8c4582a..a4b885d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -241,13 +241,12 @@ UINT8 SpdAddressTable[16]; /** Offset 0x0148 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options.\Manual: Do not use Platform Debug Consent to override other debug-relevant - policies, but the user must set each debug option manually, aimed at advanced users.\n - Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix + is viable\n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual **/ UINT8 PlatformDebugConsent; @@ -425,107 +424,107 @@ /** Offset 0x0230 - Reserved **/ - UINT8 Reserved13[2]; + UINT8 Reserved13; -/** Offset 0x0232 - Program GPIOs for LFP on DDI port-A device +/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x0233 - Program GPIOs for LFP on DDI port-B device +/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortBConfig; -/** Offset 0x0234 - Enable or disable HPD of DDI port A +/** Offset 0x0233 - Enable or disable HPD of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortAHpd; -/** Offset 0x0235 - Enable or disable HPD of DDI port B +/** Offset 0x0234 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0236 - Enable or disable HPD of DDI port C +/** Offset 0x0235 - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0237 - Enable or disable HPD of DDI port 1 +/** Offset 0x0236 - Enable or disable HPD of DDI port 1 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPort1Hpd; -/** Offset 0x0238 - Enable or disable HPD of DDI port 2 +/** Offset 0x0237 - Enable or disable HPD of DDI port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Hpd; -/** Offset 0x0239 - Enable or disable HPD of DDI port 3 +/** Offset 0x0238 - Enable or disable HPD of DDI port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Hpd; -/** Offset 0x023A - Enable or disable HPD of DDI port 4 +/** Offset 0x0239 - Enable or disable HPD of DDI port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Hpd; -/** Offset 0x023B - Enable or disable DDC of DDI port A +/** Offset 0x023A - Enable or disable DDC of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortADdc; -/** Offset 0x023C - Enable or disable DDC of DDI port B +/** Offset 0x023B - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x023D - Enable or disable DDC of DDI port C +/** Offset 0x023C - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x023E - Enable DDC setting of DDI Port 1 +/** Offset 0x023D - Enable DDC setting of DDI Port 1 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort1Ddc; -/** Offset 0x023F - Enable DDC setting of DDI Port 2 +/** Offset 0x023E - Enable DDC setting of DDI Port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Ddc; -/** Offset 0x0240 - Enable DDC setting of DDI Port 3 +/** Offset 0x023F - Enable DDC setting of DDI Port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Ddc; -/** Offset 0x0241 - Enable DDC setting of DDI Port 4 +/** Offset 0x0240 - Enable DDC setting of DDI Port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Ddc; -/** Offset 0x0242 - Reserved +/** Offset 0x0241 - Reserved **/ - UINT8 Reserved14[142]; + UINT8 Reserved14[143]; /** Offset 0x02D0 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -666,192 +665,192 @@ /** Offset 0x065D - Reserved **/ - UINT8 Reserved27[19]; + UINT8 Reserved27[91]; -/** Offset 0x0670 - Enable PCIE RP Mask +/** Offset 0x06B8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x0674 - Reserved +/** Offset 0x06BC - Reserved **/ UINT8 Reserved28[2]; -/** Offset 0x0676 - Enable HD Audio Link +/** Offset 0x06BE - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x0677 - Reserved +/** Offset 0x06BF - Reserved **/ UINT8 Reserved29[3]; -/** Offset 0x067A - Enable HD Audio DMIC_N Link +/** Offset 0x06C2 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x067C - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x06C4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x0684 - DMIC<N> ClkB Pin Muxing +/** Offset 0x06CC - DMIC<N> ClkB Pin Muxing Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x068C - Enable HD Audio DSP +/** Offset 0x06D4 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x068D - Reserved +/** Offset 0x06D5 - Reserved **/ UINT8 Reserved30[3]; -/** Offset 0x0690 - DMIC<N> Data Pin Muxing +/** Offset 0x06D8 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x0698 - Enable HD Audio SSP0 Link +/** Offset 0x06E0 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x069E - Enable HD Audio SoundWire#N Link +/** Offset 0x06E6 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x06A2 - iDisp-Link Frequency +/** Offset 0x06EA - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x06A3 - iDisp-Link T-mode +/** Offset 0x06EB - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x06A4 - iDisplay Audio Codec disconnection +/** Offset 0x06EC - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x06A5 - Debug Interfaces +/** Offset 0x06ED - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x06A6 - Serial Io Uart Debug Controller Number +/** Offset 0x06EE - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x06A7 - Reserved +/** Offset 0x06EF - Reserved **/ UINT8 Reserved31[13]; -/** Offset 0x06B4 - ISA Serial Base selection +/** Offset 0x06FC - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x06B5 - Reserved +/** Offset 0x06FD - Reserved **/ UINT8 Reserved32[4]; -/** Offset 0x06B9 - MRC Safe Config +/** Offset 0x0701 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x06BA - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x0702 - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x06BB - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x0703 - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x06BC - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x0704 - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x06BD - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x0705 - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x06BE - TCSS USB HOST (xHCI) Enable +/** Offset 0x0706 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x06BF - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x0707 - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x06C0 - TCSS DMA0 Enable +/** Offset 0x0708 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x06C1 - TCSS DMA1 Enable +/** Offset 0x0709 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x06C2 - Reserved +/** Offset 0x070A - Reserved **/ UINT8 Reserved33[2]; -/** Offset 0x06C4 - Early Command Training +/** Offset 0x070C - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x06C5 - Reserved +/** Offset 0x070D - Reserved **/ UINT8 Reserved34[65]; -/** Offset 0x0706 - Ch Hash Mask +/** Offset 0x074E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0708 - Reserved +/** Offset 0x0750 - Reserved **/ UINT8 Reserved35[64]; -/** Offset 0x0748 - PcdSerialDebugLevel +/** Offset 0x0790 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -860,70 +859,81 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0749 - Reserved +/** Offset 0x0791 - Reserved **/ UINT8 Reserved36[2]; -/** Offset 0x074B - Safe Mode Support +/** Offset 0x0793 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x074C - Reserved +/** Offset 0x0794 - Reserved **/ UINT8 Reserved37[2]; -/** Offset 0x074E - TCSS USB Port Enable +/** Offset 0x0796 - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x074F - Reserved +/** Offset 0x0797 - Reserved **/ UINT8 Reserved38[50]; -/** Offset 0x0781 - Skip external display device scanning +/** Offset 0x07C9 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0782 - Reserved +/** Offset 0x07CA - Reserved **/ UINT8 Reserved39; -/** Offset 0x0783 - Lock PCU Thermal Management registers +/** Offset 0x07CB - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0784 - Reserved +/** Offset 0x07CC - Reserved **/ UINT8 Reserved40[129]; -/** Offset 0x0805 - Skip CPU replacement check +/** Offset 0x084D - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0806 - Reserved +/** Offset 0x084E - Reserved **/ UINT8 Reserved41[292]; -/** Offset 0x092A - Serial Io Uart Debug Mode +/** Offset 0x0972 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x092B - Reserved +/** Offset 0x0973 - Reserved **/ - UINT8 Reserved42[517]; + UINT8 Reserved42[183]; + +/** Offset 0x0A2A - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0A2B - Reserved +**/ + UINT8 Reserved43[349]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -943,11 +953,11 @@ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B30 +/** Offset 0x0B88 **/ - UINT8 UnusedUpdSpace32[6]; + UINT8 UnusedUpdSpace33[6]; -/** Offset 0x0B36 +/** Offset 0x0B8E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 7ec577a..685eeeb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -80,6 +80,7 @@ #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ typedef struct { @@ -121,107 +122,111 @@ **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x0072 - Enable USB2 ports +/** Offset 0x0072 - Reserved +**/ + UINT8 Reserved2[34]; + +/** Offset 0x0094 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x0082 - Enable USB3 ports +/** Offset 0x00A4 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x008C - Enable xDCI controller +/** Offset 0x00AE - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x008D - Reserved +/** Offset 0x00AF - Reserved **/ - UINT8 Reserved2[28]; + UINT8 Reserved3[26]; -/** Offset 0x00A9 - Enable SATA +/** Offset 0x00C9 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x00AA - SATA Mode +/** Offset 0x00CA - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x00AB - SPIn Device Mode +/** Offset 0x00CB - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[7]; -/** Offset 0x00B2 - Reserved +/** Offset 0x00D2 - Reserved **/ - UINT8 Reserved3[35]; + UINT8 Reserved4[35]; -/** Offset 0x00D5 - SPIn Default Chip Select Mode HW/SW +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW **/ UINT8 SerialIoSpiCsMode[7]; -/** Offset 0x00DC - SPIn Default Chip Select State Low/High +/** Offset 0x00FC - SPIn Default Chip Select State Low/High Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High **/ UINT8 SerialIoSpiCsState[7]; -/** Offset 0x00E3 - UARTn Device Mode +/** Offset 0x0103 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x00EA - Reserved +/** Offset 0x010A - Reserved **/ - UINT8 Reserved4[65]; + UINT8 Reserved5[65]; -/** Offset 0x012B - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0132 - Reserved +/** Offset 0x0152 - Reserved **/ - UINT8 Reserved5[2]; + UINT8 Reserved6[2]; -/** Offset 0x0134 - SerialIoUartRtsPinMuxPolicy +/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartRtsPinMuxPolicy[7]; -/** Offset 0x0150 - SerialIoUartCtsPinMuxPolicy +/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values. **/ UINT32 SerialIoUartCtsPinMuxPolicy[7]; -/** Offset 0x016C - SerialIoUartRxPinMuxPolicy +/** Offset 0x018C - SerialIoUartRxPinMuxPolicy Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values. **/ UINT32 SerialIoUartRxPinMuxPolicy[7]; -/** Offset 0x0188 - SerialIoUartTxPinMuxPolicy +/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values. **/ UINT32 SerialIoUartTxPinMuxPolicy[7]; -/** Offset 0x01A4 - UART Number For Debug Purpose +/** Offset 0x01C4 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. @@ -229,169 +234,169 @@ **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x01A5 - Reserved +/** Offset 0x01C5 - Reserved **/ - UINT8 Reserved6[7]; + UINT8 Reserved7[7]; -/** Offset 0x01AC - I2Cn Device Mode +/** Offset 0x01CC - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x01B4 - Serial IO I2C SDA Pin Muxing +/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x01D4 - Serial IO I2C SCL Pin Muxing +/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x01F4 - Reserved +/** Offset 0x0214 - Reserved **/ - UINT8 Reserved7[192]; + UINT8 Reserved8[192]; -/** Offset 0x02B4 - USB Per Port HS Preemphasis Bias +/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2PhyPetxiset[16]; -/** Offset 0x02C4 - USB Per Port HS Transmitter Bias +/** Offset 0x02E4 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2PhyTxiset[16]; -/** Offset 0x02D4 - USB Per Port HS Transmitter Emphasis +/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2PhyPredeemp[16]; -/** Offset 0x02E4 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2PhyPehalfbit[16]; -/** Offset 0x02F4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x02FE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x0308 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x0312 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x031C - Reserved +/** Offset 0x033C - Reserved **/ - UINT8 Reserved8[80]; + UINT8 Reserved9[80]; -/** Offset 0x036C - Enable LAN +/** Offset 0x038C - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x036D - Reserved +/** Offset 0x038D - Reserved **/ - UINT8 Reserved9[11]; + UINT8 Reserved10[11]; -/** Offset 0x0378 - PCIe PTM enable/disable +/** Offset 0x0398 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. **/ UINT8 PciePtm[28]; -/** Offset 0x0394 - Reserved +/** Offset 0x03B4 - Reserved **/ - UINT8 Reserved10[81]; + UINT8 Reserved11[81]; -/** Offset 0x03E5 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage +/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. **/ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; -/** Offset 0x03E6 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage +/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; -/** Offset 0x03E7 - Reserved +/** Offset 0x0407 - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved12; -/** Offset 0x03E8 - Transition time in microseconds from Off (0V) to High Current Mode Voltage +/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x03EA - Reserved +/** Offset 0x040A - Reserved **/ - UINT8 Reserved12[50]; + UINT8 Reserved13[50]; -/** Offset 0x041C - CNVi Configuration +/** Offset 0x043C - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x041D - CNVi BT Core +/** Offset 0x043D - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x041E - CNVi BT Audio Offload +/** Offset 0x043E - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x041F - Reserved +/** Offset 0x043F - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved14; -/** Offset 0x0420 - CNVi RF_RESET pin muxing - Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) - or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +/** Offset 0x0440 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0424 - CNVi CLKREQ pin muxing - Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) - or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in - GpioPins*.h. +/** Offset 0x0444 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* + in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x0428 - Reserved +/** Offset 0x0448 - Reserved **/ - UINT8 Reserved14[166]; + UINT8 Reserved15[174]; -/** Offset 0x04CE - CdClock Frequency selection +/** Offset 0x04F6 - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, @@ -399,293 +404,297 @@ **/ UINT8 CdClock; -/** Offset 0x04CF - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x04F7 - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x04D0 - Enable D3 Hot in TCSS +/** Offset 0x04F8 - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x04D1 - Reserved +/** Offset 0x04F9 - Reserved **/ - UINT8 Reserved15[3]; + UINT8 Reserved16[3]; -/** Offset 0x04D4 - TypeC port GPIO setting +/** Offset 0x04FC - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl = AlderLake) **/ UINT32 IomTypeCPortPadCfg[8]; -/** Offset 0x04F4 - Reserved +/** Offset 0x051C - Reserved **/ - UINT8 Reserved16[8]; + UINT8 Reserved17[8]; -/** Offset 0x04FC - Enable D3 Cold in TCSS +/** Offset 0x0524 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x04FD - Reserved +/** Offset 0x0525 - Reserved **/ - UINT8 Reserved17[8]; + UINT8 Reserved18[8]; -/** Offset 0x0505 - Enable VMD controller +/** Offset 0x052D - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x0506 - Reserved +/** Offset 0x052E - Reserved **/ - UINT8 Reserved18[108]; + UINT8 Reserved19[120]; -/** Offset 0x0572 - TCSS Aux Orientation Override Enable +/** Offset 0x05A6 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x0574 - TCSS HSL Orientation Override Enable +/** Offset 0x05A8 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x0576 - Reserved +/** Offset 0x05AA - Reserved **/ - UINT8 Reserved19[2]; + UINT8 Reserved20[2]; -/** Offset 0x0578 - ITBT Root Port Enable +/** Offset 0x05AC - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x057C - Reserved +/** Offset 0x05B0 - Reserved **/ - UINT8 Reserved20[2]; + UINT8 Reserved21[2]; -/** Offset 0x057E - ITbtConnectTopology Timeout value +/** Offset 0x05B2 - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x0580 - Reserved +/** Offset 0x05B4 - Reserved **/ - UINT8 Reserved21[7]; + UINT8 Reserved22[7]; -/** Offset 0x0587 - Enable/Disable PTM +/** Offset 0x05BB - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x058B - Reserved +/** Offset 0x05BF - Reserved **/ - UINT8 Reserved22[201]; + UINT8 Reserved23[200]; -/** Offset 0x0654 - Skip Multi-Processor Initialization +/** Offset 0x0687 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0655 - Reserved +/** Offset 0x0688 - Reserved **/ - UINT8 Reserved23[11]; + UINT8 Reserved24[8]; -/** Offset 0x0660 - CpuMpPpi +/** Offset 0x0690 - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x0664 - Reserved +/** Offset 0x0694 - Reserved **/ - UINT8 Reserved24[68]; + UINT8 Reserved25[70]; -/** Offset 0x06A8 - Enable Power Optimizer +/** Offset 0x06DA - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x06A9 - Reserved +/** Offset 0x06DB - Reserved **/ - UINT8 Reserved25[33]; + UINT8 Reserved26[33]; -/** Offset 0x06CA - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x06CB - Reserved +/** Offset 0x06FD - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved27[2]; -/** Offset 0x06CD - Enable PCH ISH SPI pins assigned +/** Offset 0x06FF - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x06CE - Enable PCH ISH UART pins assigned +/** Offset 0x0700 - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x06D0 - Enable PCH ISH I2C pins assigned +/** Offset 0x0702 - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x06D3 - Enable PCH ISH GP pins assigned +/** Offset 0x0705 - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[8]; -/** Offset 0x06DB - Reserved +/** Offset 0x070D - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; -/** Offset 0x06DD - Enable LOCKDOWN BIOS LOCK +/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x06DE - Reserved +/** Offset 0x0710 - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved29[2]; -/** Offset 0x06E0 - RTC Cmos Memory Lock +/** Offset 0x0712 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x06E1 - Enable PCIE RP HotPlug +/** Offset 0x0713 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[28]; -/** Offset 0x06FD - Reserved +/** Offset 0x072F - Reserved **/ - UINT8 Reserved29[56]; + UINT8 Reserved30[56]; -/** Offset 0x0735 - Enable PCIE RP Clk Req Detect +/** Offset 0x0767 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x0751 - PCIE RP Advanced Error Report +/** Offset 0x0783 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x076D - Reserved +/** Offset 0x079F - Reserved **/ - UINT8 Reserved30[196]; + UINT8 Reserved31[196]; -/** Offset 0x0831 - PCIE RP Max Payload +/** Offset 0x0863 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[28]; -/** Offset 0x084D - Touch Host Controller Port 0 Assignment +/** Offset 0x087F - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x084E - Reserved +/** Offset 0x0880 - Reserved **/ - UINT8 Reserved31[6]; + UINT8 Reserved32[5]; -/** Offset 0x0854 - Touch Host Controller Port 1 Assignment +/** Offset 0x0885 - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x0855 - Reserved +/** Offset 0x0886 - Reserved **/ - UINT8 Reserved32[91]; + UINT8 Reserved33[91]; -/** Offset 0x08B0 - PCIE RP Aspm +/** Offset 0x08E1 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[28]; -/** Offset 0x08CC - PCIE RP L1 Substates +/** Offset 0x08FD - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x08E8 - PCIE RP Ltr Enable +/** Offset 0x0919 - Reserved +**/ + UINT8 Reserved34[28]; + +/** Offset 0x0935 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0904 - Reserved +/** Offset 0x0951 - Reserved **/ - UINT8 Reserved33[102]; + UINT8 Reserved35[105]; -/** Offset 0x096A - PCH Sata Pwr Opt Enable +/** Offset 0x09BA - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x096B - Reserved +/** Offset 0x09BB - Reserved **/ - UINT8 Reserved34[50]; + UINT8 Reserved36[50]; -/** Offset 0x099D - Enable SATA Port DmVal +/** Offset 0x09ED - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x09A5 - Reserved +/** Offset 0x09F5 - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved37; -/** Offset 0x09A6 - Enable SATA Port DmVal +/** Offset 0x09F6 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x09B6 - Reserved +/** Offset 0x0A06 - Reserved **/ - UINT8 Reserved36[62]; + UINT8 Reserved38[62]; -/** Offset 0x09F4 - USB2 Port Over Current Pin +/** Offset 0x0A44 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A04 - USB3 Port Over Current Pin +/** Offset 0x0A54 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A0E - Reserved +/** Offset 0x0A5E - Reserved **/ - UINT8 Reserved37[14]; + UINT8 Reserved39[14]; -/** Offset 0x0A1C - Enable 8254 Static Clock Gating +/** Offset 0x0A6C - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -693,7 +702,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A1D - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A6D - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -701,22 +710,22 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A1E - Reserved +/** Offset 0x0A6E - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved40; -/** Offset 0x0A1F - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A6F - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A20 - Reserved +/** Offset 0x0A70 - Reserved **/ - UINT8 Reserved39[113]; + UINT8 Reserved41[113]; -/** Offset 0x0A91 - Enable PS_ON. +/** Offset 0x0AE1 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -724,29 +733,29 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0A92 - Reserved +/** Offset 0x0AE2 - Reserved **/ - UINT8 Reserved40[310]; + UINT8 Reserved42[310]; -/** Offset 0x0BC8 - RpPtmBytes +/** Offset 0x0C18 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0BCC - Reserved +/** Offset 0x0C1C - Reserved **/ - UINT8 Reserved41[99]; + UINT8 Reserved43[99]; -/** Offset 0x0C2F - Enable/Disable IGFX PmSupport +/** Offset 0x0C7F - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C30 - Reserved +/** Offset 0x0C80 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved44; -/** Offset 0x0C31 - GT Frequency Limit +/** Offset 0x0C81 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -760,22 +769,22 @@ **/ UINT8 GtFreqMax; -/** Offset 0x0C32 - Reserved +/** Offset 0x0C82 - Reserved **/ - UINT8 Reserved43[24]; + UINT8 Reserved45[24]; -/** Offset 0x0C4A - Enable or Disable HWP +/** Offset 0x0C9A - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C4B - Reserved +/** Offset 0x0C9B - Reserved **/ - UINT8 Reserved44[8]; + UINT8 Reserved46[8]; -/** Offset 0x0C53 - TCC Activation Offset +/** Offset 0x0CA3 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -783,63 +792,63 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0C54 - Reserved +/** Offset 0x0CA4 - Reserved **/ - UINT8 Reserved45[34]; + UINT8 Reserved47[34]; -/** Offset 0x0C76 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CC6 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0C77 - Reserved +/** Offset 0x0CC7 - Reserved **/ - UINT8 Reserved46[197]; + UINT8 Reserved48[197]; -/** Offset 0x0D3C - Enable LOCKDOWN SMI +/** Offset 0x0D8C - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D3D - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D8D - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D3E - Unlock all GPIO pads +/** Offset 0x0D8E - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D3F - Reserved +/** Offset 0x0D8F - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved49; -/** Offset 0x0D40 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D90 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; + UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0D70 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DC8 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0DA0 - Reserved +/** Offset 0x0E00 - Reserved **/ - UINT8 Reserved48[289]; + UINT8 Reserved50[313]; -/** Offset 0x0EC1 - LpmStateEnableMask +/** Offset 0x0F39 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0EC2 - Reserved +/** Offset 0x0F3A - Reserved **/ - UINT8 Reserved49[766]; + UINT8 Reserved51[766]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -858,11 +867,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x11C0 +/** Offset 0x1238 **/ - UINT8 UnusedUpdSpace49[6]; + UINT8 UnusedUpdSpace48[6]; -/** Offset 0x11C6 +/** Offset 0x123E **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/46695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Gerrit-Change-Number: 46695 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: broadwell: Switch to using common ACPI _SWS code
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/11647 ) Change subject: broadwell: Switch to using common ACPI _SWS code ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/11647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14 Gerrit-Change-Number: 11647 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

1 0

Change in coreboot[master]: broadwell: update processor power limits configuration
by Sumeet R Pawnikar (Code Review) 25 Oct '20

25 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41234 ) Change subject: broadwell: update processor power limits configuration ...................................................................... broadwell: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Broadwell SoC based platforms. BRANCH=None BUG=None TEST=Build for broadwell based platform Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/msr.h A src/soc/intel/broadwell/include/soc/soc_chip.h M src/soc/intel/broadwell/systemagent.c 8 files changed, 33 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41234/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 20219d3..67f7563 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER @@ -34,10 +35,12 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT - select CPU_INTEL_COMMON select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 8afdba1..e44a1a1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -25,6 +25,7 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> +#include <intelblocks/cpulib.h> /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 7351d70..c8df32d 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -5,6 +5,7 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include <drivers/intel/gma/i915.h> +#include <intelblocks/cfg.h> #include <stdint.h> struct soc_intel_broadwell_config { diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 35df1b5..f5ec878 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -17,6 +17,7 @@ #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <intelblocks/cpulib.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -26,64 +27,6 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ @@ -289,90 +232,6 @@ RCBA32(PMSYNC_CONFIG2) = pmsync2; } -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on server SKU */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 93d8a01..90ea613 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -38,10 +38,6 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 7328f19..ab97b90 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -4,6 +4,8 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ +#include <intelblocks/msr.h> + #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -46,14 +48,6 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h new file mode 100644 index 0000000..ff77168 --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/soc_chip.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BROADWELL_SOC_CHIP_H_ +#define _SOC_BROADWELL_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index ac1008b..5adb731 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -405,6 +406,7 @@ static void systemagent_init(struct device *dev) { + struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -424,7 +426,8 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); } static struct device_operations systemagent_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Gerrit-Change-Number: 41234 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: nb/intel/haswell/gma.c: Drop space after unary `!`
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46691 ) Change subject: nb/intel/haswell/gma.c: Drop space after unary `!` ...................................................................... nb/intel/haswell/gma.c: Drop space after unary `!` Change-Id: I72f75f3df50af362874818f2c1883a6a1c741087 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46691/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index dc7b629..989d100 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -485,7 +485,7 @@ } } - if (! lightup_ok) { + if (!lightup_ok) { printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); mdelay(CONFIG_PRE_GRAPHICS_DELAY); pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f75f3df50af362874818f2c1883a6a1c741087 Gerrit-Change-Number: 46691 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: nb/intel/haswell/gma.c: Move log message to the right place
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46690 ) Change subject: nb/intel/haswell/gma.c: Move log message to the right place ...................................................................... nb/intel/haswell/gma.c: Move log message to the right place The message was being printed too early, possibly because it was relocated around alongside the rest of the code. Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46690/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2368e7b..dc7b629 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -290,8 +290,6 @@ struct northbridge_intel_haswell_config *conf = config_of(dev); u32 reg32; - printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { @@ -493,7 +491,8 @@ pci_dev_init(dev); } - /* Post panel init */ + printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); + gma_pm_init_post_vbios(dev); gma_enable_swsci(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6 Gerrit-Change-Number: 46690 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel`
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46689 ) Change subject: nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel` ...................................................................... nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel` This is to reduce differences between Haswell and Broadwell. Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46689/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 5a6bb8e..2368e7b 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -287,7 +287,7 @@ static void gma_setup_panel(struct device *dev) { - struct northbridge_intel_haswell_config *conf = dev->chip_info; + struct northbridge_intel_haswell_config *conf = config_of(dev); u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/46689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90 Gerrit-Change-Number: 46689 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/broadwell/gma.c: Align `igd_setup_panel` with Haswell
by Angel Pons (Code Review) 25 Oct '20

25 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46688 ) Change subject: soc/intel/broadwell/gma.c: Align `igd_setup_panel` with Haswell ...................................................................... soc/intel/broadwell/gma.c: Align `igd_setup_panel` with Haswell Rename it, add a print and factor out refclock value into a variable. Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/gma.c 1 file changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46688/1 diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index ba453cdb2..8ccd278 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -281,7 +281,7 @@ return 0; } -static void igd_setup_panel(struct device *dev) +static void gma_setup_panel(struct device *dev) { config_t *conf = config_of(dev); u32 reg32; @@ -326,7 +326,8 @@ Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ - const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + const unsigned int refclock = 24 * MHz; + const unsigned int hz_limit = refclock / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken2; @@ -340,7 +341,12 @@ } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + printk(BIOS_INFO, + "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", + refclock / MHz, pwm_increment, pwm_period, + DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period)); + /* Start with a 50% duty cycle. */ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); @@ -532,7 +538,7 @@ gtt_write(0xa008, rp1_gfx_freq << 24); /* Post VBIOS panel setup */ - igd_setup_panel(dev); + gma_setup_panel(dev); /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2 Gerrit-Change-Number: 46688 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020