coreboot-gerrit October 2020

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Change in coreboot[master]: nb/intel/gm45: Clean up header handling
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45452 ) Change subject: nb/intel/gm45: Clean up header handling ...................................................................... nb/intel/gm45: Clean up header handling There's no need to have ACPI guards in `gm45.h`, since the only things the ASL files require are the base address definitions in `memmap.h`. Also, remove the southbridge include from `gm45.h` and place it only in the files that actually require something from it. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c 4 files changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45452/1 diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..e4d8d66 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../gm45.h" +#include "../memmap.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e362841..86f71d6 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -2,6 +2,7 @@ #include <stdint.h> #include <device/pci_ops.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index cad0596..7c4b22b 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include <southbridge/intel/i82801ix/i82801ix.h> - -#ifndef __ACPI__ - #include <stdint.h> typedef enum { @@ -163,8 +159,6 @@ VCO_5333 = 2, }; -#endif - /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ @@ -345,8 +339,6 @@ #include "registers/epbar.h" -#ifndef __ACPI__ - void gm45_early_init(void); void gm45_early_reset(void); @@ -396,5 +388,4 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 9d30c5b..6472a29 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Gerrit-Change-Number: 45452 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Introduce memmap.h
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45451 ) Change subject: nb/intel/gm45: Introduce memmap.h ...................................................................... nb/intel/gm45: Introduce memmap.h Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/memmap.h 2 files changed, 17 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45451/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 061bf2d..cad0596 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -170,16 +170,7 @@ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ - -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 - - -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#include "memmap.h" /* * D0:F0 diff --git a/src/northbridge/intel/gm45/memmap.h b/src/northbridge/intel/gm45/memmap.h new file mode 100644 index 0000000..b778f2d --- /dev/null +++ b/src/northbridge/intel/gm45/memmap.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ + +#define DEFAULT_MCHBAR 0xfed14000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 + + +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 + +#endif /* __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Gerrit-Change-Number: 45451 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Add more DMIBAR/EPBAR registers
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45448 ) Change subject: nb/intel/gm45: Add more DMIBAR/EPBAR registers ...................................................................... nb/intel/gm45: Add more DMIBAR/EPBAR registers Add definitions for more DMIBAR/EPBAR registers, and specify their sizes as well. Also, expand a comment as the registers' purpose is now known. On loops that poll these registers, move the semicolon to a new line. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/raminit.c 3 files changed, 78 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45448/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 91e6326..31c6984 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -361,15 +361,29 @@ #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ /* * EPBAR @@ -379,11 +393,30 @@ #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index c82e1d6..9d30c5b 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -10,34 +10,36 @@ static void init_egress(void) { /* VC0: TC0 only */ - EPBAR8(0x14) &= 1; - EPBAR8(0x4) = (EPBAR8(0x4) & ~7) | 1; + EPBAR8(EPVC0RCTL) &= 1; + EPBAR8(EPPVCCAP1) = (EPBAR8(EPPVCCAP1) & ~7) | 1; /* VC1: isoch */ - EPBAR32(0x28) = 0x0a0a0a0a; - EPBAR32(0x1c) = (EPBAR32(0x1c) & ~(127 << 16)) | (0x0a << 16); + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~(127 << 16)) | (0x0a << 16); /* VC1: ID1, TC7 */ - EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); - EPBAR8(0x20) = (EPBAR8(0x20) & 1) | (1 << 7); + EPBAR32(EPVC1RCTL) = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); + EPBAR8(EPVC1RCTL) = (EPBAR8(EPVC1RCTL) & 1) | (1 << 7); /* VC1 ARB table: setup and enable */ - EPBAR32(0x100) = 0x55555555; - EPBAR32(0x104) = 0x55555555; - EPBAR32(0x108) = 0x55555555; - EPBAR32(0x10c) = 0x55555555; - EPBAR32(0x110) = 0x55555555; - EPBAR32(0x114) = 0x55555555; - EPBAR32(0x118) = 0x55555555; - EPBAR32(0x11c) = 0x00005555; - EPBAR32(0x20) |= 1 << 16; + EPBAR32(EP_PORTARB(0)) = 0x55555555; + EPBAR32(EP_PORTARB(1)) = 0x55555555; + EPBAR32(EP_PORTARB(2)) = 0x55555555; + EPBAR32(EP_PORTARB(3)) = 0x55555555; + EPBAR32(EP_PORTARB(4)) = 0x55555555; + EPBAR32(EP_PORTARB(5)) = 0x55555555; + EPBAR32(EP_PORTARB(6)) = 0x55555555; + EPBAR32(EP_PORTARB(7)) = 0x00005555; + EPBAR32(EPVC1RCTL) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0); + while ((EPBAR8(EPVC1RSTS) & 1) != 0) + ; /* VC1: enable */ - EPBAR32(0x20) |= 1 << 31; + EPBAR32(EPVC1RCTL) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0); + while ((EPBAR8(EPVC1RSTS) & 2) != 0) + ; } /* MCH side */ @@ -46,16 +48,17 @@ { /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) &= 1; - DMIBAR8(0x4) = (DMIBAR8(0x4) & ~7) | 1; + DMIBAR8(DMIPVCCAP1) = (DMIBAR8(DMIPVCCAP1) & ~7) | 1; /* VC1: ID1, TC7 */ - DMIBAR32(0x20) = (DMIBAR32(0x20) & ~(7 << 24)) | (1 << 24); - DMIBAR8(0x20) = (DMIBAR8(0x20) & 1) | (1 << 7); + DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); + DMIBAR8(DMIVC1RCTL) = (DMIBAR8(DMIVC1RCTL) & 1) | (1 << 7); /* VC1: enable */ - DMIBAR32(0x20) |= 1 << 31; + DMIBAR32(DMIVC1RCTL) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0); + while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0) + ; /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; @@ -224,11 +227,11 @@ the endpoint (ICH), but ICH doesn't give any limits. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) - DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once) + DMIBAR8(DMILCTL) |= (3 << 0); // enable ASPM L0s, L1 (write-once) else - DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once) + DMIBAR8(DMILCTL) |= (1 << 0); // enable ASPM L0s (write-once) /* timing */ - DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15); + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~(63 << 12)) | (2 << 12) | (2 << 15); DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b95e563..5975b80 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1130,7 +1130,7 @@ } } -/* Program egress VC1 timings. */ +/* Program egress VC1 isoch timings. */ static void vc1_program_timings(const fsb_clock_t fsb) { const u32 timings_by_fsb[][2] = { @@ -1138,9 +1138,9 @@ /* FSB 800MHz */ { 0x14, 0x00f000f0 }, /* FSB 667MHz */ { 0x10, 0x00c000c0 }, }; - EPBAR8(0x2c) = timings_by_fsb[fsb][0]; - EPBAR32(0x38) = timings_by_fsb[fsb][1]; - EPBAR32(0x3c) = timings_by_fsb[fsb][1]; + EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0]; + EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1]; + EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1]; } #define DEFAULT_PCI_MMIO_SIZE 2048 -- To view, visit https://review.coreboot.org/c/coreboot/+/45448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Gerrit-Change-Number: 45448 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Add more host bridge PCI IDs
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45562 ) Change subject: nb/intel/ironlake: Add more host bridge PCI IDs ...................................................................... nb/intel/ironlake: Add more host bridge PCI IDs The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. The current coreboot code seems to be able to change the device ID of the host bridge, but it seems to be missing a warm reset so that the device ID changes. Account for the 'mysterious' device IDs in the northbridge driver, so that booting an OS has a chance to work. Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45562/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index cf014fe..e0e926e 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -202,10 +202,34 @@ .ops_pci = &pci_dev_ops_pci, }; +/* + * The host bridge PCI device ID can be changed by the firmware. There + * is no documentation about it, though. There's 'official' IDs, which + * appear in spec updates and Windows drivers, and 'mysterious' IDs, + * which Intel doesn't want OSes to know about and thus are not listed. + * + * The current coreboot code seems to be able to change the device ID + * of the host bridge, but it seems to be missing a warm reset so that + * the device ID changes. Account for the 'mysterious' device IDs in + * the northbridge driver, so that booting an OS has a chance to work. + */ +static const unsigned short pci_device_ids[] = { + /* 'Official' DIDs */ + 0x0040, /* Clarkdale */ + 0x0044, /* Arrandale */ + 0x0048, /* Unknown, but it appears in OS drivers and raminit */ + + /* Mysterious DIDs, taken from Linux' intel-agp driver */ + 0x0062, /* Clarkdale A-? */ + 0x0069, /* Clarkdale K-0 */ + 0x006a, /* Arrandale K-0 */ + 0 +}; + static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Arrandale DRAM controller */ + .device = pci_device_ids, }; static struct device_operations cpu_bus_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Gerrit-Change-Number: 45562 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Generalise northbridge chip name
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46664 ) Change subject: nb/intel/ironlake: Generalise northbridge chip name ...................................................................... nb/intel/ironlake: Generalise northbridge chip name The code is known to work on processors other than just i7's. Also, use the northbridge's name (Ironlake) in place of the CPU's (Arrandale). Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46664/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 2cffa29..0047c2f 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -225,7 +225,7 @@ } struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") + CHIP_NAME("Intel Ironlake integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a Gerrit-Change-Number: 46664 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Generalise northbridge chip name
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46663 ) Change subject: nb/intel/haswell: Generalise northbridge chip name ...................................................................... nb/intel/haswell: Generalise northbridge chip name The code is known to work on processors other than just i7's. Change-Id: I8be83bf51315547b29ab2b239e953554d3a323a0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46663/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9cf564f..88ccd71 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -638,6 +638,6 @@ } struct chip_operations northbridge_intel_haswell_ops = { - CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") + CHIP_NAME("Intel Haswell integrated Northbridge") .enable_dev = enable_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be83bf51315547b29ab2b239e953554d3a323a0 Gerrit-Change-Number: 46663 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: haswell: Set up Root Complex topology
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43744 ) Change subject: haswell: Set up Root Complex topology ...................................................................... haswell: Set up Root Complex topology System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it. Tested on Asrock B85M Pro4, still boots. Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index baa4f32..e6dfe3a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -91,6 +91,11 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0) +/* Device 0:1.0 PCI configuration space (PCIe Graphics Attach) */ +#define PEG_DCAP2 0xc4 /* 32bit */ +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -144,6 +149,10 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */ #define PORTARB 0x100 /* 256bit */ @@ -169,6 +178,8 @@ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define DMIESD 0x044 /* 32bit */ + #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ #define DMILE2D 0x060 /* 32bit */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4311710..25ed828 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -453,12 +453,80 @@ DMIBAR8(0xd34) = 0x44; } +static void northbridge_topology_init(void) +{ + struct device *dev; + + /* Set the CID1 EP Port Root Topology */ + EPBAR32(EPESD) = (1 << 16); + + EPBAR32(EPLE1D) = (1 << 16) | 1; + EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + dev = pcidev_on_root(1, 0); + if (dev && dev->enabled) { + + EPBAR32(EPLE2A) = 0x8000; + EPBAR32(EPLE2D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 1); + if (dev && dev->enabled) { + + EPBAR32(EPLE3A) = 0x9000; + EPBAR32(EPLE3D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 2); + if (dev && dev->enabled) { + + EPBAR32(EPLE4A) = 0xa000; + EPBAR32(EPLE4D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + DMIBAR32(DMIESD) = (1 << 16) | 1; + + DMIBAR32(DMILE1D) = (2 << 16) | 1; + DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR32(DMILE2D) = (1 << 16) | 1; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; - if (!CONFIG(INTEL_LYNXPOINT_LP)) + if (!CONFIG(INTEL_LYNXPOINT_LP)) { northbridge_dmi_init(); + northbridge_topology_init(); + } /* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b0..85fab4d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -19,6 +19,7 @@ #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> +#include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> @@ -500,6 +501,18 @@ RCBA32_OR(0x21a8, 0x3); } +static void pch_topology_init(void) +{ + /* Set component id to 2 for southbridge, northbridge has id 1 */ + RCBA32(ESD) = (2 << 16); + + /* Set target port number and target component id of the northbridge */ + RCBA32(ULD) = (1 << 24) | (1 << 16); + + /* Set target RCRB base address, i.e. DMIBAR */ + RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -546,6 +559,8 @@ pch_set_acpi_mode(); pch_fixups(dev); + + pch_topology_init(); } static void pch_lpc_add_mmio_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/43744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Gerrit-Change-Number: 43744 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: correct Legacy 8254 Timer Kconfig help text
by Angel Pons (Code Review) 24 Oct '20

24 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46414 ) Change subject: soc/intel/common: correct Legacy 8254 Timer Kconfig help text ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22bd4ab88fbd215a0eb7900c2d05dde565e4be1f Gerrit-Change-Number: 46414 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Oct 2020 15:42:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Michael Niewöhner (Code Review) 24 Oct '20

24 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Well. Sure that actually works? > > > > > > The pmtimer is used in case seabios runs on qemu and initializes the (virtual) acpi pci device. > > > I doubt this also happens when running as coreboot payload. > > > > I have reason to assume it does: > > > > platform_hardware_setup() calls coreboot_platform_setup() calls > > find_acpi_features() calls pmtimer_setup(). Didn't test it though, > > but I assume the PM timer would be used. > > > > And the PM timer always works as it's emulated in the worst case :) > > Thanks Nico, I'll test that once again Meh. Testing this again, I noticed that with PIT disabled SeaBIOS does not auto-boot from disk after ~ 2 sec anymore. To make it work again I had to disable CONFIG_HARDWARE_IRQ. That means, somehow the PIC (code) depends on PIT -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Oct 2020 15:35:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: FSP 2.0: Add fsp_relax_security
by Michael Niewöhner (Code Review) 24 Oct '20

24 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25437 ) Change subject: FSP 2.0: Add fsp_relax_security ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/notify.c: https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/… PS18, Line 70: __attribute__((weak)) bool fsp_relax_security(void) instead of *another* callback, why not have a Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/25437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Gerrit-Change-Number: 25437 Gerrit-PatchSet: 20 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 24 Oct 2020 14:08:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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