coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sridhar Siricilla (Code Review) 26 Oct '20

26 Oct '20

Sridhar Siricilla has uploaded a new patch set (#54) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 8 files changed, 659 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 54 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/edid: Add missing name descriptor presence flag.
by Name of user not set (Code Review) 26 Oct '20

26 Oct '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46694 ) Change subject: lib/edid: Add missing name descriptor presence flag. ...................................................................... lib/edid: Add missing name descriptor presence flag. EDID parser internal flah c->has_name_descriptor flag was never set. It was causing decode_edid() function to return NON_CONFORMANT instead of CONFORMANT even when EDID frame was correct. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289 --- M src/lib/edid.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46694/1 diff --git a/src/lib/edid.c b/src/lib/edid.c index f20d239..cd7a47a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -261,6 +261,7 @@ extract_string(x + 5, &c->has_valid_string_termination, EDID_ASCII_STRING_LENGTH)); + c->has_name_descriptor = 1; return 1; case 0xFD: { -- To view, visit https://review.coreboot.org/c/coreboot/+/46694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289 Gerrit-Change-Number: 46694 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 26 Oct '20

26 Oct '20

Arthur Heymans has uploaded a new patch set (#21) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM save state MSR don't work, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 13 files changed, 206 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 21 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI ti...
by Michael Niewöhner (Code Review) 26 Oct '20

26 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#31). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 18 files changed, 5 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Michael Niewöhner (Code Review) 26 Oct '20

26 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Michał Żygowski, Frans Hendriks, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph, Wim Vervoorn, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45955 to look at the new patch set (#29). Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 41 files changed, 41 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45955/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 29 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 26 Oct '20

26 Oct '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#21). Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... soc/intel: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. TODO: test this patch on APL hardware to prove this assumption ^ Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 13 files changed, 36 insertions(+), 167 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Michael Niewöhner (Code Review) 26 Oct '20

26 Oct '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46464 to look at the new patch set (#19). Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... cpu/intel/common: correct MSR for the Nominal Performance in CPPC The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 2 files changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46464/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 26 Oct '20

26 Oct '20

Arthur Heymans has uploaded a new patch set (#20) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - Verified on Deltalake mainboard. - SMI's are properly generated and handled Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 13 files changed, 250 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 20 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool: Don't build unneeded commonlib sources
by Julius Werner (Code Review) 26 Oct '20

26 Oct '20

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46253 ) Change subject: cbfstool: Don't build unneeded commonlib sources ...................................................................... cbfstool: Don't build unneeded commonlib sources These sources are built but not used by cbfstool. The only .c file in commonlib/ it really needs is fsp_relocate.c. Get rid of the others. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9 --- M util/cbfstool/Makefile.inc 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46253/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index bc2ff48..ca1d79e 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -23,10 +23,7 @@ cbfsobj += xdr.o cbfsobj += partitioned_file.o # COMMONLIB -cbfsobj += cbfs.o cbfsobj += fsp_relocate.o -cbfsobj += mem_pool.o -cbfsobj += region.o # FMAP cbfsobj += fmap.o cbfsobj += kv_pair.o @@ -72,10 +69,6 @@ ifitobj += cbfs-mkstage.o ifitobj += cbfs-mkpayload.o ifitobj += rmodule.o -# COMMONLIB -ifitobj += cbfs.o -ifitobj += mem_pool.o -ifitobj += region.o # FMAP ifitobj += fmap.o ifitobj += kv_pair.o @@ -205,10 +198,6 @@ $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-unused-function # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -# Tolerate commonlib warnings -$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes $(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes -- To view, visit https://review.coreboot.org/c/coreboot/+/46253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9 Gerrit-Change-Number: 46253 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: vboot: Disable vboot functions in SMM
by Julius Werner (Code Review) 26 Oct '20

26 Oct '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46645 to review the following change. Change subject: vboot: Disable vboot functions in SMM ...................................................................... vboot: Disable vboot functions in SMM SMM does not have access to CBMEM and therefore cannot access any persistent state like the vboot context. This makes it impossible to query vboot state like the developer mode switch or the currently active RW CBFS. However some code (namely the PC80 option table) does CBFS accesses in SMM. This is currently worked around by directly using cbfs_locate_file_in_region() with the COREBOOT region. By disabling vboot functions explicitly in SMM, we can get rid of that and use normal CBFS APIs in this code. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377 --- M src/security/vboot/vboot_common.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46645/1 diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index f2cff65..e64f663 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -45,7 +45,7 @@ void verstage_mainboard_init(void); /* Check boot modes */ -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) && !ENV_SMM int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); int vboot_can_enable_udc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377 Gerrit-Change-Number: 46645 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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