coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Werner Zeh (Code Review) 27 Oct '20

27 Oct '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 21: > Patch Set 21: > > I don't have any APL hardware either... Werner do you have time to verify this patch? Hey Tim, let's see how good our bot already is 😊 start siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 27 Oct 2020 07:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
by Jonathan Zhang (Code Review) 27 Oct '20

27 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46711 ) Change subject: cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN ...................................................................... cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN Fix CID 1435825 and 1435826. The CIDs discovered Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46711/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 284a113..cb7ecdc 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -484,9 +484,9 @@ * size. The maximum size is calculated by a function of the * min base bit set and maximum size bit set. */ if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; + mtrr_size = 1ULL << size_msb; else - mtrr_size = 1 << addr_lsb; + mtrr_size = 1ULL << addr_lsb; if (var_state->prepare_msrs) prep_var_mtrr(var_state, base, mtrr_size, mtrr_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/46711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 Gerrit-Change-Number: 46711 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 27 Oct '20

27 Oct '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 10: register "policies.active" = "{ : [0] = {.target = DPTF_CPU, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [1] = {.target = DPTF_TEMP_SENSOR_0, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [2] = {.target = DPTF_TEMP_SENSOR_1, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [3] = {.target = DPTF_TEMP_SENSOR_2, : .thresholds = {TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0), : TEMP_PCT(0, 0),}}, : [4] = {.target = DPTF_TEMP_SENSOR_3, : .thresholds = {TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" > I believe this can be changed to register "policies.active" = "{ […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 27 Oct 2020 05:51:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 27 Oct '20

27 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#7). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 27 Oct '20

27 Oct '20

Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#6). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/kukui: fix SKUID config for burnet/esche
by Kevin Chiu (Code Review) 27 Oct '20

27 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46442 ) Change subject: mb/google/kukui: fix SKUID config for burnet/esche ...................................................................... mb/google/kukui: fix SKUID config for burnet/esche ADCIN2 (LCM_ID) now was PD 200K but we might get incorrect voltage in different condition: developer mode ADC[2]: Raw value=232459 ID=1 recovery mode: ADC[2]: Raw value=36144 ID=0 in order to match sku definition of burnet/esche: burnet: 0x11 esche: 0x10 we'll need to bypass ADCIN2 to update SKUID accordingly. BUG=b:170916885 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. check burnet/esche skuid correctly Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46442/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 548f36b..71df979 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -96,6 +96,11 @@ } } + if (CONFIG(BOARD_GOOGLE_BURNET)) { + cached_sku_id = (0x10 | get_adc_index(SKU_ID_CHANNEL)); + return cached_sku_id; + } + /* * The SKU (later used for device tree matching) is combined from: * ADC2[4bit/H] = straps on LCD module (type of panel). -- To view, visit https://review.coreboot.org/c/coreboot/+/46442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446 Gerrit-Change-Number: 46442 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/asurada: Init dram in romstage
by CK HU (Code Review) 27 Oct '20

27 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44568 to review the following change. Change subject: mb/google/asurada: Init dram in romstage ...................................................................... mb/google/asurada: Init dram in romstage Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/romstage.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44568/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 8395e4a..c742539 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -8,6 +8,7 @@ romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += memlayout.ld diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c new file mode 100644 index 0000000..8fa2f38 --- /dev/null +++ b/src/mainboard/google/asurada/romstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/dramc_param.h> +#include <soc/emi.h> +#include <soc/mmu_operations.h> + +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "read data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "write data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter = {0x0}; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + +void platform_romstage_main(void) +{ + mt_mem_init(&dparam_ops); + mtk_mmu_after_dram(); + printk(BIOS_WARNING, "after mt_mem_init\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Gerrit-Change-Number: 44568 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update variant specific GPIOs for boldar
by Aamir Bohra (Code Review) 27 Oct '20

27 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46828 ) Change subject: mb/google/volteer: Update variant specific GPIOs for boldar ...................................................................... mb/google/volteer: Update variant specific GPIOs for boldar boldar has EC_IN_RW mapped to GPP_A8 which differs from baseboard configuration. Hence boldar gpio cannot use the baseboard defined gpio mappings as is. Update the variant specific GPIO mapping for boldar and remove direct include of baseboard gpio.h owing to configuration deltas. Change-Id: Iba20b1636a155f4bf4bd9a50a015c9b73809cec3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46828/1 diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h index c4fe342..789c90a8 100644 --- a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h @@ -3,6 +3,25 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H -#include <baseboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_A8 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_B11 + +/* EC wake is LAN_WAKE# */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_C6_IRQ + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* DRAM population strap (value 0=fully-populated, 1=half-populated) */ +#define GPIO_MEM_CH_SEL GPP_A17 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba20b1636a155f4bf4bd9a50a015c9b73809cec3 Gerrit-Change-Number: 46828 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Tim Wawrzynczak (Code Review) 26 Oct '20

26 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 21: I don't have any APL hardware either... Werner do you have time to verify this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 26 Oct 2020 22:45:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Tim Wawrzynczak (Code Review) 26 Oct '20

26 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 18: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/c/coreboot/+/46465/18/src/soc/intel/skylake/acp… PS18, Line 377: 2 nit: a `#define CPPC_VERSION 2` or similar would be more readable -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Oct 2020 22:42:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020