coreboot-gerrit October 2020

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Change in coreboot[master]: util/docker: Update coreboot-sdk consolidate coreboot build
by Martin Roth (Code Review) 27 Oct '20

27 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46801 ) Change subject: util/docker: Update coreboot-sdk consolidate coreboot build ...................................................................... util/docker: Update coreboot-sdk consolidate coreboot build Because docker saves a container for every run command, by breaking the coreboot build into 3 commands, it greatly increased the size of the docker containers needed. When combined as one run command, the coreboot repo that is downloaded, along with the coreboot test build are deleted before the container is created. Since those directories are deleted in a later run command, they don't even make it into the final container, and just force coreboot-sdk users to download extra data for no reason. While splitting the build may help with debugging failures when creating the docker container, that debugging can be done locally by splitting up a working copy. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46801/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 0ae63c8..3946814 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -84,21 +84,17 @@ && ln -s /usr/bin/aclocal /usr/bin/aclocal-1.15 RUN \ - cd /root && \ + cd /tmp && \ git clone https://review.coreboot.org/coreboot && \ cd coreboot && \ - git checkout {{DOCKER_COMMIT}} - -RUN \ + git checkout {{DOCKER_COMMIT}}; \ if echo {{CROSSGCC_PARAM}} | grep -q ^all; then \ - make -C/root/coreboot/util/crossgcc/ build_clang \ + make -C /tmp/coreboot/util/crossgcc/ build_clang \ BUILD_LANGUAGES=c,ada CPUS=$(nproc) DEST=/opt/xgcc; \ - fi - -RUN \ - make -C/root/coreboot/util/crossgcc/ {{CROSSGCC_PARAM}} \ + fi; \ + make -C /tmp/coreboot/util/crossgcc/ {{CROSSGCC_PARAM}} \ BUILD_LANGUAGES=c,ada CPUS=$(nproc) DEST=/opt/xgcc && \ - rm -rf /root/coreboot + rm -rf /tmp/coreboot RUN mkdir /home/coreboot/.ccache && \ chown coreboot:coreboot /home/coreboot/.ccache && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/46801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca Gerrit-Change-Number: 46801 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/docker: Update coreboot-sdk with additional tools
by Martin Roth (Code Review) 27 Oct '20

27 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46799 ) Change subject: util/docker: Update coreboot-sdk with additional tools ...................................................................... util/docker: Update coreboot-sdk with additional tools - cscope: Run cscope targets - ctags: Run ctags targets - pbzip2: Allow compression on all cpu cores Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979 --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46799/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 007e9af..749b543 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -24,11 +24,13 @@ bzip2 \ ccache \ cmake \ + cscope \ curl \ device-tree-compiler \ dh-autoreconf \ diffutils \ doxygen \ + exuberant-ctags \ flex \ g++ \ gawk \ @@ -62,6 +64,7 @@ nasm \ openssl \ patch \ + pbzip2 \ pkg-config \ python2 \ python3 \ -- To view, visit https://review.coreboot.org/c/coreboot/+/46799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979 Gerrit-Change-Number: 46799 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/auron: Prepare devicetree for PCH split
by Angel Pons (Code Review) 27 Oct '20

27 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46702 ) Change subject: mb/google/auron: Prepare devicetree for PCH split ...................................................................... mb/google/auron: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, TODO. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 7 files changed, 135 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46702/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a309762..09593b7 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,27 +15,6 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - register "s0ix_enable" = "1" device cpu_cluster 0 on @@ -46,40 +25,64 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + +# chip soc/intel/broadwell/pch + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sio_acpi_mode" = "1" + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal +# end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 60aef30..dc70085 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index da80fec..b46e34c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f148964..45229ba 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,32 +7,34 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "sata_devslp_disable" = "0x1" - - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - register "s0ix_enable" = "0" device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus +# chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus +# end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 75c202d..eae7999 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 60aef30..dc70085 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index c5d2747..710fa95 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,30 +10,32 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - register "sata_port0_gen3_tx" = "0x72" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" # Disable S0ix for now register "s0ix_enable" = "0" - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 15.3 on end # GSPI0 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - device pci 1d.0 off end # USB2 EHCI +# chip soc/intel/broadwell/pch + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI +# end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Gerrit-Change-Number: 46702 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/testing: Remove test for util/broadcom/secimage
by Martin Roth (Code Review) 27 Oct '20

27 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46805 ) Change subject: util/testing: Remove test for util/broadcom/secimage ...................................................................... util/testing: Remove test for util/broadcom/secimage util/broadcom/secimage was removed in commit aea00f496b1, so don't try to test it anymore. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92 --- M util/testing/Makefile.inc 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46805/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index fb36c71..494055e 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -115,8 +115,6 @@ @echo "Build testing $(TOOLLIST)" $(foreach tool, $(TOOLLIST), $(MAKE) -C util/$(tool) clean ; ) $(foreach tool, $(TOOLLIST), echo "Building $(tool)";export MFLAGS= ;export MAKEFLAGS= ;$(MAKE) -C util/$(tool) all V=$(V) Q=$(Q) || exit 1; ) - echo "Testing broadcom/secimage" - $(MAKE) -C util/broadcom/secimage test @echo "Running gitconfig tests" @for test in $$(find util/gitconfig/test -maxdepth 1 \ -type f -executable); do \ -- To view, visit https://review.coreboot.org/c/coreboot/+/46805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92 Gerrit-Change-Number: 46805 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Werner Zeh (Code Review) 27 Oct '20

27 Oct '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 21: Code-Review+1 Patch was tested on mc_apl1 and mc_apl4 without issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Oct 2020 09:31:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) 27 Oct '20

27 Oct '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/amd/picasso/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 27 Oct '20

27 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45701 ) Change subject: soc/amd/picasso/acpi: Convert to ASL 2.0 syntax ...................................................................... soc/amd/picasso/acpi: Convert to ASL 2.0 syntax Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/pci_int.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/sleepstates.asl 4 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45701/1 diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index eb646de..e1b7498 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -48,7 +48,7 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 8)) { + If (\PCNT >= 8) { Return (Package () { \_SB.C000, @@ -60,7 +60,7 @@ \_SB.C006, \_SB.C007 }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { + } ElseIf (\PCNT >= 4) { Return (Package () { \_SB.C000, @@ -68,7 +68,7 @@ \_SB.C002, \_SB.C003 }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { + } ElseIf (\PCNT >= 2) { Return (Package () { \_SB.C000, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 2a2a561..8114c52 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -3,7 +3,7 @@ Method(\_PIC, 0x01, NotSerialized) { printf("PIC MODE: %o", Arg0) - Store(Arg0, PMOD) + PMOD = Arg0 } /* PIC Possible Resource Values */ diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 9208e13..f627a28 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -9,14 +9,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -78,15 +78,15 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) - Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) + BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index 88c6efc..03d28bb 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -3,25 +3,25 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) If (CONFIG(HAVE_ACPI_RESUME)) { - Store(0x0D, SSFG) + SSFG = 0x0D } If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSFG & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/45701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Gerrit-Change-Number: 45701 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Werner Zeh (Code Review) 27 Oct '20

27 Oct '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 21: One more try start siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 27 Oct 2020 08:16:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Werner Zeh (Code Review) 27 Oct '20

27 Oct '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 21: Bot is still not working properly...I will investigate and re-trigger. -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 27 Oct 2020 07:27:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Werner Zeh (Code Review) 27 Oct '20

27 Oct '20

Werner Zeh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Removed Verified-1 by siemens-bot (1003096) -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: deleteVote

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