coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Tim Wawrzynczak (Code Review) 23 Oct '20

23 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/45747/7/src/ec/google/chromeec/chi… File src/ec/google/chromeec/chip.h: https://review.coreboot.org/c/coreboot/+/45747/7/src/ec/google/chromeec/chi… PS7, Line 6: #include <stddef.h> > #include <device/device. […] Done https://review.coreboot.org/c/coreboot/+/45747/8/src/ec/google/chromeec/ec_… File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/45747/8/src/ec/google/chromeec/ec_… PS8, Line 138: for (i = 0; i < num_ports; ++i) { > Should there be a check here: […] I'm not sure if we should bail or attempt to write as much as we know about, I'm inclined to think we should write as much as we can; downstream code will deal with the NULL, and this information is all included in _DSD so the kernel should be able to deal with not finding a node. -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 23 Oct 2020 21:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Add ECC config reporting
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46367 ) Change subject: soc/intel/broadwell: Add ECC config reporting ...................................................................... soc/intel/broadwell: Add ECC config reporting This has been taken from Haswell, and is just to reduce differences. Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/romstage/raminit.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46367/1 diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 4977b35..98002c6 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -21,6 +21,13 @@ #include <soc/romstage.h> #include <soc/systemagent.h> +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + /* * Dump in the log memory controller configuration as read from the memory * controller registers. @@ -46,7 +53,7 @@ u32 ch_conf = addr_decode_ch[i]; printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); -- To view, visit https://review.coreboot.org/c/coreboot/+/46367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a Gerrit-Change-Number: 46367 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Remove unnecessary array
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46369 ) Change subject: soc/intel/broadwell: Remove unnecessary array ...................................................................... soc/intel/broadwell: Remove unnecessary array The MAD_DIMM registers can be read within the loop just fine. Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/romstage/raminit.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46369/1 diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 6d3ee31..af3e473 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -87,6 +87,9 @@ #define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) +/* Memory controller characteristics */ +#define NUM_CHANNELS 2 + #define MAD_CHNL 0x5000 #define MAD_DIMM(ch) (0x5004 + 4 * (ch)) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 98002c6..7020ddf 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -34,12 +34,9 @@ */ static void report_memory_config(void) { - u32 addr_decode_ch[2]; int i; const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -49,8 +46,8 @@ (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; + for (i = 0; i < NUM_CHANNELS; i++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); -- To view, visit https://review.coreboot.org/c/coreboot/+/46369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Gerrit-Change-Number: 46369 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Fix copy-pasted copy-paste error
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46366 ) Change subject: soc/intel/broadwell: Fix copy-pasted copy-paste error ...................................................................... soc/intel/broadwell: Fix copy-pasted copy-paste error The code with this error was copy-pasted from Haswell. It was fixed with commit dab81a4 (northbridge/intel/haswell: Fix copy paste error) for Haswell. Do the same for Broadwell. Given that LP SKUs only support one DIMM per channel, this change makes no difference in practice. Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/romstage/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46366/1 diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 00419fc..4977b35 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -61,7 +61,7 @@ printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23 Gerrit-Change-Number: 46366 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Add missing MCHBAR register definitions
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46364 ) Change subject: soc/intel/broadwell: Add missing MCHBAR register definitions ...................................................................... soc/intel/broadwell: Add missing MCHBAR register definitions Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/romstage/raminit.c 2 files changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46364/1 diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 5a52590..6d3ee31 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -87,7 +87,10 @@ #define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR_PEI_VERSION 0x5034 +#define MAD_CHNL 0x5000 +#define MAD_DIMM(ch) (0x5004 + 4 * (ch)) + +#define MRC_REVISION 0x5034 #define MC_LOCK 0x50fc @@ -133,6 +136,8 @@ #define BIOS_RESET_CPL 0x5da8 +#define MC_BIOS_DATA 0x5e04 + #define SAPMCTL 0x5f00 #define HDAUDRID 0x6008 diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index fb780cf..7b0e22f 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -30,12 +30,12 @@ u32 addr_decoder_common, addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, @@ -128,7 +128,7 @@ die("pei_data version mismatch\n"); /* Print the MRC version after executing the UEFI PEI stage. */ - u32 version = MCHBAR32(MCHBAR_PEI_VERSION); + u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); -- To view, visit https://review.coreboot.org/c/coreboot/+/46364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466 Gerrit-Change-Number: 46364 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Relocate `report_memory_config` function
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46360 ) Change subject: soc/intel/broadwell: Relocate `report_memory_config` function ...................................................................... soc/intel/broadwell: Relocate `report_memory_config` function This allows us to make it static, like it is on Haswell. Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c 3 files changed, 41 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46360/1 diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index f45419c..721e23f 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -19,7 +19,6 @@ struct chipset_power_state; struct chipset_power_state *fill_power_state(void); void report_platform_info(void); -void report_memory_config(void); void set_max_freq(void); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 0580ca6..fb780cf 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -22,6 +22,47 @@ #include <soc/systemagent.h> /* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + +/* * Find PEI executable in coreboot filesystem and execute it. */ void raminit(struct pei_data *pei_data) diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 938f3eb..4ed84d7 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -180,44 +180,3 @@ report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9 Gerrit-Change-Number: 46360 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/romstage/pch.c: Drop reg-script usage
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46359 ) Change subject: soc/intel/broadwell/romstage/pch.c: Drop reg-script usage ...................................................................... soc/intel/broadwell/romstage/pch.c: Drop reg-script usage Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/romstage/pch.c 1 file changed, 21 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46359/1 diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 9afb4e4..d68e17e 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -4,7 +4,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> @@ -15,7 +14,8 @@ #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h> -const struct reg_script pch_interrupt_init_script[] = { +static void pch_route_interrupts(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -28,38 +28,26 @@ */ /* Device interrupt pin register (board specific) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP, - (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP, - (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */ - DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */ - DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */ - DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */ - DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */ - DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */ - DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */ - DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */ - DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)), - - REG_SCRIPT_END -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ +} static void pch_enable_lpc(void) { @@ -76,7 +64,7 @@ void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); + pch_route_interrupts(); pch_enable_lpc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Gerrit-Change-Number: 46359 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/romstage/romstage.c: Clean up includes
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46358 ) Change subject: soc/intel/broadwell/romstage/romstage.c: Clean up includes ...................................................................... soc/intel/broadwell/romstage/romstage.c: Clean up includes Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ibbffe152e511065dc265155555c56446fbb70405 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/romstage/romstage.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46358/1 diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 83e5b73..35792f3 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <acpi/acpi.h> #include <arch/romstage.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <elog.h> -#include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> #include <soc/gpio.h> @@ -14,7 +11,7 @@ #include <soc/pei_data.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/spi.h> +#include <stdint.h> /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/46358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbffe152e511065dc265155555c56446fbb70405 Gerrit-Change-Number: 46358 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add settings for noise mitgation
by Shaunak Saha (Code Review) 23 Oct '20

23 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45053 ) Change subject: mb/google/volteer: Add settings for noise mitgation ...................................................................... mb/google/volteer: Add settings for noise mitgation Enable acoustic noise mitgation for volteer platform. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45053/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ffae2f0..5e33f41 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -232,6 +232,17 @@ register "tcc_offset" = "10" # TCC of 90 + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[0]" = "2" + register "SlowSlewRate[1]" = "2" + register "SlowSlewRate[2]" = "2" + register "SlowSlewRate[3]" = "2" + register "FastPkgCRampDisable[0]" = "1" + register "FastPkgCRampDisable[1]" = "1" + register "FastPkgCRampDisable[2]" = "1" + register "FastPkgCRampDisable[3]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/45053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 Gerrit-Change-Number: 45053 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add Acoustic features
by Shaunak Saha (Code Review) 23 Oct '20

23 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45052 ) Change subject: soc/intel/tigerlake: Add Acoustic features ...................................................................... soc/intel/tigerlake: Add Acoustic features Expose the following FSP UPD interface into coreboot, which is the following: AcousticNoiseMitigation FastPkgCRampDisable SlowSlewRateFor AcousticNoiseMitigation is the UPD for Acoustic Noise Mitigation. FastPkgCRampDisable UPD's are to disable Fast Slew Rate for Deep Package C States for VR domains. SlowSlewRate UPD's are the Slew Rate configuration for Deep Package C States for VR domains. Slew rates are fast time divided by 2. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45052/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2da63ed..8d2483e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -145,6 +145,35 @@ /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* + * Acoustic Noise Mitigation + * 0 - Disable + * 1 - Enable noise mitigation + */ + uint8_t AcousticNoiseMitigation; + + /* + * Offset 0x054B - Disable Fast Slew Rate for Deep Package + * C States for VR domains. Disable Fast Slew Rate for Deep + * Package C States based on Acoustic Noise Mitigation feature + * enabled. + * 0 - False + * 1 - True + */ + uint8_t FastPkgCRampDisable[5]; + + /* + * Offset 0x0550 - Slew Rate configuration for Deep Package + * C States for VR domains. Slew Rate configuration for Deep + * Package C States for VR domains based on Acoustic Noise + * Mitigation feature enabled. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ + uint8_t SlowSlewRate[5]; + /* SATA related */ uint8_t SataEnable; uint8_t SataMode; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1601c2c..39baa67 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -247,6 +247,13 @@ } } + params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + for (i = 0; i < ARRAY_SIZE(config->SlowSlewRate); i++) + params->SlowSlewRate[i] = config->SlowSlewRate[i]; + + for (i = 0; i < ARRAY_SIZE(config->FastPkgCRampDisable); i++) + params->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; + /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/45052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Gerrit-Change-Number: 45052 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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