coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: nb/intel/sandybridge: Correct designation of MRC version
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46372 ) Change subject: nb/intel/sandybridge: Correct designation of MRC version ...................................................................... nb/intel/sandybridge: Correct designation of MRC version Do not use `System Agent version` to refer to the MRC version, which is what the register being printed contains under normal circumstances. Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46372/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 697862f..444ecf8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -176,9 +176,9 @@ if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); - /* For reference, print the System Agent version after executing the UEFI PEI stage */ + /* Print the MRC version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); - printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", + printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, (version >> 0) & 0xff); -- To view, visit https://review.coreboot.org/c/coreboot/+/46372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29 Gerrit-Change-Number: 46372 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/haswell: Correct designation of MRC version
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46371 ) Change subject: nb/intel/haswell: Correct designation of MRC version ...................................................................... nb/intel/haswell: Correct designation of MRC version Do not use `System Agent version` to refer to the MRC version, which is what the register being printed contains under normal circumstances. Use the code from Broadwell, which also happens to be indented with tabs. Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46371/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index ea3e0a7..c17841c 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -161,11 +161,11 @@ die("UEFI PEI System Agent not found.\n"); } - /* For reference, print the System Agent version after executing the UEFI PEI stage */ + /* Print the MRC version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); - printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - (version >> 24) & 0xff, (version >> 16) & 0xff, - (version >> 8) & 0xff, (version >> 0) & 0xff); + printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088 Gerrit-Change-Number: 46371 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/haswell: Drop ASM to call into MRC
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46370 ) Change subject: nb/intel/haswell: Drop ASM to call into MRC ...................................................................... nb/intel/haswell: Drop ASM to call into MRC Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.) did it for Sandy Bridge, and this commit does it for Haswell. The original assembly is identical for both platforms, so this should work. Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46370/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 6db5e71..ea3e0a7 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -105,7 +105,8 @@ */ void sdram_initialize(struct pei_data *pei_data) { - unsigned long entry; + int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); + uint32_t type = CBFS_TYPE_MRC; struct cbfsf f; @@ -134,11 +135,9 @@ die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); + entry = rdev_mmap_full(&f.data); if (entry) { - int rv; - asm volatile ("call *%%ecx\n\t" - :"=a" (rv) : "c" (entry), "a" (pei_data)); + int rv = entry(pei_data); /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) -- To view, visit https://review.coreboot.org/c/coreboot/+/46370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29 Gerrit-Change-Number: 46370 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/haswell: Constify pointers to strings
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46368 ) Change subject: nb/intel/haswell: Constify pointers to strings ...................................................................... nb/intel/haswell: Constify pointers to strings Jenkins complains about it. Change-Id: I20abdd01ca2b93e8a4de31664ff48651e7268d25 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46368/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 5a39e60..6db5e71 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -51,7 +51,7 @@ pei_data->mrc_input, mrc_size); } -static const char *ecc_decoder[] = { +static const char *const ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", -- To view, visit https://review.coreboot.org/c/coreboot/+/46368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20abdd01ca2b93e8a4de31664ff48651e7268d25 Gerrit-Change-Number: 46368 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/haswell: Make MAD_DIMM_* registers indexed
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46362 ) Change subject: nb/intel/haswell: Make MAD_DIMM_* registers indexed ...................................................................... nb/intel/haswell: Make MAD_DIMM_* registers indexed This allows using the macro in a loop, for instance. Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46362/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index aaeaadf..7fd6b3f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -65,8 +65,8 @@ int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -227,8 +227,8 @@ memset(mem_info, 0, sizeof(struct memory_info)); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index d6e59ab..60e16e0 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -5,9 +5,7 @@ /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ +#define MAD_DIMM(ch) (0x5004 + (ch) * 4) #define MC_INIT_STATE_G 0x5030 #define MRC_REVISION 0x5034 /* MRC Revision */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb Gerrit-Change-Number: 46362 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/haswell: Drop unnecessary register read
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46361 ) Change subject: nb/intel/haswell: Drop unnecessary register read ...................................................................... nb/intel/haswell: Drop unnecessary register read Reading MAD_CHNL has no effect, so there's no need to read it here. Change-Id: I8d2aa4787de7f54f49d161f61c9c0abaa811cb83 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46361/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00f..aaeaadf 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -227,8 +227,6 @@ memset(mem_info, 0, sizeof(struct memory_info)); - /* FIXME: Do we need to read MCHBAR32(MAD_CHNL) ? (Answer: Nope) */ - MCHBAR32(MAD_CHNL); addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2aa4787de7f54f49d161f61c9c0abaa811cb83 Gerrit-Change-Number: 46361 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46356 ) Change subject: soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro ...................................................................... soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/memmap.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46356/1 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index fb9a834..e4c787a 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -35,8 +35,8 @@ void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); - uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG); + uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM); tseg = ALIGN_DOWN(tseg, 1 * MiB); bgsm = ALIGN_DOWN(bgsm, 1 * MiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/46356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd Gerrit-Change-Number: 46356 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/broadwell: Use common early SMBus code
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46355 ) Change subject: soc/intel/broadwell: Use common early SMBus code ...................................................................... soc/intel/broadwell: Use common early SMBus code Disabling interrupts and clearing errors was being done twice, once in the `smbus_enable_iobar` reg-script, and another in `enable_smbus`. Change-Id: I58558996bd693b302764965a5bed8b96db363833 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/romstage/Makefile.inc D src/soc/intel/broadwell/romstage/smbus.c 3 files changed, 1 insertion(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46355/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 0ea5dbd..35129af 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -17,6 +17,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index a53cd95..edfec30 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -5,6 +5,5 @@ romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-y += smbus.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c deleted file mode 100644 index a000255..0000000 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_def.h> -#include <device/smbus_host.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> -#include <soc/romstage.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -uintptr_t smbus_base(void) -{ - return SMBUS_BASE_ADDRESS; -} - -int smbus_enable_iobar(uintptr_t base) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58558996bd693b302764965a5bed8b96db363833 Gerrit-Change-Number: 46355 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46351 ) Change subject: soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init ...................................................................... soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/lpc.c 1 file changed, 53 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46351/1 diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 495f134..7adb926 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -172,33 +172,65 @@ enable_alt_smi(config->alt_gp_smi_en); } -static const struct reg_script pch_misc_init_script[] = { - /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ - REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), - (1 << 3)|(1 << 11)|(1 << 12)), +static void pch_misc_init(struct device *dev) +{ + u8 reg8; + u16 reg16; + u32 reg32; + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + /* Prepare sleep mode */ - REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), + reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 &= ~SLP_TYP; + reg32 |= SCI_EN; + outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + + /* Set up NMI on errors */ + reg8 = inb(0x61); + reg8 &= ~0xf0; /* Higher nibble must be 0 */ + reg8 |= (1 << 2); /* PCI SERR# disable for now */ + outb(reg8, 0x61); + /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), + reg8 = inb(0x70); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + outb(reg8, 0x70); + /* Indicate DRAM init done for MRC */ - REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); + /* Enable BIOS updates outside of SMM */ - REG_PCI_RMW8(0xdc, ~(1 << 5), 0), + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + /* Clear status bits to prevent unexpected wake */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + RCBA32_OR(0x3310, 0x2f); + + RCBA32_AND_OR(0x3f02, ~0xf, 0); + /* Enable PCIe Releaxed Order */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), + RCBA32_OR(0x2314, (1 << 31) | (1 << 7)), + RCBA32_OR(0x1114, (1 << 15) | (1 << 14)), + /* Setup SERIRQ, enable continuous mode */ - REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !CONFIG(SERIRQ_CONTINUOUS_MODE) - REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), -#endif - REG_SCRIPT_END -}; + reg8 = pci_read_config8(dev, SERIRQ_CNTL); + reg8 |= 1 << 7; + + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + reg8 |= 1 << 6; + + pci_write_config8(dev, SERIRQ_CNTL, reg8); +} /* Magic register settings for power management */ static void pch_pm_init_magic(struct device *dev) @@ -427,7 +459,7 @@ /* Legacy initialization */ isa_dma_init(); sb_rtc_init(); - reg_script_run_on_dev(dev, pch_misc_init_script); + pch_misc_init(dev); /* Interrupt configuration */ pch_enable_ioapic(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d Gerrit-Change-Number: 46351 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init
by Angel Pons (Code Review) 23 Oct '20

23 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46350 ) Change subject: soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init ...................................................................... soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/lpc.c 1 file changed, 65 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46350/1 diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b3f4fe5..495f134 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -201,59 +201,71 @@ }; /* Magic register settings for power management */ -static const struct reg_script pch_pm_init_script[] = { - REG_PCI_WRITE8(0xa9, 0x46), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101), - REG_PCI_RMW32(0xac, ~0x00200000, 0), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), +static void pch_pm_init_magic(struct device *dev) +{ + pci_write_config8(dev, 0xa9, 0x46); + + RCBA32_AND_OR(0x232c, ~1, 0); + + RCBA32_OR(0x1100, 0x0000c13f); + + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + + RCBA32(0x3314) = 0x00012fff; + + RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400); + + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3368) = 0x00041400; + RCBA32(0x3388) = 0x3f8ddbff; + RCBA32(0x33ac) = 0x00007001; + RCBA32(0x33b0) = 0x00181900; + RCBA32(0x33c0) = 0x00060A00; + RCBA32(0x33d0) = 0x06200840; + RCBA32(0x3a28) = 0x01010101; + RCBA32(0x3a2c) = 0x040c0404; + RCBA32(0x3a9c) = 0x9000000a; + RCBA32(0x2b1c) = 0x03808033; + RCBA32(0x2b34) = 0x80000009; + RCBA32(0x3348) = 0x022ddfff; + RCBA32(0x334c) = 0x00000001; + RCBA32(0x3358) = 0x0001c000; + RCBA32(0x3380) = 0x3f8ddbff; + RCBA32(0x3384) = 0x0001c7e1; + RCBA32(0x338c) = 0x0001c7e1; + RCBA32(0x3398) = 0x0001c000; + RCBA32(0x33a8) = 0x00181900; + RCBA32(0x33dc) = 0x00080000; + RCBA32(0x33e0) = 0x00000001; + RCBA32(0x3a20) = 0x0000040c; + RCBA32(0x3a24) = 0x01010101; + RCBA32(0x3a30) = 0x01010101; + + pci_update_config32(dev, 0xac, ~0x00200000, 0); + + RCBA32_OR(0x0410, 0x00000003); + RCBA32_OR(0x2618, 0x08000000); + RCBA32_OR(0x2300, 0x00000002); + RCBA32_OR(0x2600, 0x00000008); + + RCBA32(0x33b4) = 0x00007001; + RCBA32(0x3350) = 0x022ddfff; + RCBA32(0x3354) = 0x00000001; + /* Power Optimizer */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000), - REG_SCRIPT_END -}; + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; + RCBA32(0x3a80) = 0x05145005; + RCBA32(0x3a84) = 0x00001005; + + RCBA32_OR(0x33d4, 0x2fff2fb1); + RCBA32_OR(0x33c8, 0x00008000); +} static void pch_enable_mphy(void) { @@ -320,7 +332,7 @@ pch_enable_mphy(); - reg_script_run_on_dev(dev, pch_pm_init_script); + pch_pm_init_magic(dev); if (pch_is_wpt()) { RCBA32_OR(0x33e0, (1 << 4) | (1 << 1)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5 Gerrit-Change-Number: 46350 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020