coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Zhuohao Lee (Code Review) 23 Oct '20

23 Oct '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 63: .pl1 = {.min_power = 15000, : .max_power = 15000, PL1 min max set to the same value looks weird. I'm not quite sure if this is reasonable. https://review.coreboot.org/c/coreboot/+/46676/4/src/mainboard/google/volte… PS4, Line 68: .pl2 = {.min_power = 51000, : .max_power = 51000, as here. -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 23 Oct 2020 12:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK: asurada: mainboard: Set pinctrl for msdc0/emmc
by Yidi Lin (Code Review) 23 Oct '20

23 Oct '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46384 to review the following change. Change subject: HACK: asurada: mainboard: Set pinctrl for msdc0/emmc ...................................................................... HACK: asurada: mainboard: Set pinctrl for msdc0/emmc For some reason I can't do that correctly in kernel. BUG=none TEST=boot asurada, lsblk shows /dev/mmcblk0 Change-Id: I921f8c4d75c96c89ec0bc8df8f66b9af789adf97 --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46384/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 9146d7b..b77b3ba 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -2,10 +2,62 @@ #include <console/console.h> #include <device/device.h> +#include <device/mmio.h> +#include <lib.h> +#include <soc/gpio_common.h> #include <soc/usb.h> +static void sdr_set_field(void *addr, u32 field, u32 val) +{ + u32 tv = read32(addr); + + tv &= ~field; + tv |= ((val) << (__ffs(field))); + write32(addr, tv); +} + static void mainboard_init(struct device *dev) { + int i; + + /* HACK, set pinctrl for SD card */ + for (i = 51; i <= 56; i++) + gpio_set_mode((gpio_t){.id = i}, 1); + + /* HACK, set pinctrl for eMMC */ + for (i = 183; i <= 194; i++) + gpio_set_mode((gpio_t){.id = i}, 1); + + + /** MSDC1 **/ + /*emmc pupd*/ + volatile uint32_t *pupd = (volatile uint32_t *)0x11C20060; + printk(BIOS_ERR, "pupd = %04x\n", *pupd); + *pupd = 0xfc1; + printk(BIOS_ERR, "pupd = %04x\n", *pupd); + + /*emmc driving*/ + volatile uint32_t *driv = (volatile uint32_t *)0x11C20000; + printk(BIOS_ERR, "driv = %04x\n", *driv); + *driv = 0x09249000 << 1; + printk(BIOS_ERR, "driv = %04x\n", *driv); + +// sdr_set_field(host->gpio_base, 0x3fffffff, 0x24924924); + + /** MSDC0 **/ + void *gpio_base = (void *)IOCFG_TL_BASE; + /*emmc ies*/ + sdr_set_field(gpio_base + 0x20, 0xFFF, 0xFFF); + /*emmc smt*/ + sdr_set_field(gpio_base + 0x90, 0xFFF, 0xFFF); + /*emmc pupd*/ + sdr_set_field(gpio_base + 0x30, 0x7ff, 0x401); + sdr_set_field(gpio_base + 0x40, 0x7ff, 0x3FE); + sdr_set_field(gpio_base + 0x50, 0x7fff, 0x401); + + /*emmc driving*/ + sdr_set_field(gpio_base, 0x3fffffff, 0x24924924); + setup_usb_host(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921f8c4d75c96c89ec0bc8df8f66b9af789adf97 Gerrit-Change-Number: 46384 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 23 Oct '20

23 Oct '20

Hello build bot (Jenkins), Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#4). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 23 Oct '20

23 Oct '20

Hello Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46676 to look at the new patch set (#3). Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=None TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46676/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 23 Oct '20

23 Oct '20

Frank Chu has restored this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: restore

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 23 Oct '20

23 Oct '20

Frank Chu has removed Zhuohao Lee from this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Removed reviewer Zhuohao Lee. -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters f...
by Frank Chu (Code Review) 23 Oct '20

23 Oct '20

Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: UPSTREAM: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
by Michael Niewöhner (Code Review) 23 Oct '20

23 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46461 ) Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC ...................................................................... Patch Set 11: > Patch Set 11: Code-Review+1 > > > Well, I'm not sure if it's really worth adding a function for two checks, where one will vanish soon (when SKL uses common acpi code). I could add it, though > > How is this done in common ACPI code? see CB:45535. I guess Nico's point was, that were doing the same check in SKL and common code, so we could have one function somewhere to use it in both. -- To view, visit https://review.coreboot.org/c/coreboot/+/46461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Gerrit-Change-Number: 46461 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 06:45:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
by Frans Hendriks (Code Review) 23 Oct '20

23 Oct '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46462 ) Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Gerrit-Change-Number: 46462 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Oct 2020 06:40:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: enable RECOVERY_MRC_CACHE
by Shelley Chen (Code Review) 23 Oct '20

23 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46651 ) Change subject: sc7180: enable RECOVERY_MRC_CACHE ...................................................................... sc7180: enable RECOVERY_MRC_CACHE Enable caching of memory training data for recovery as well as normal mode because memory training is taking too long in recovery as well. This required creating a space in the fmap for RECOVERY_MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=Run power_state:rec twice on lazor. Ensure that on first boot, memory training occurs and on second boot, memory training is skipped. Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig 3 files changed, 10 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46651/1 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index d5324ee..e7985f2 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -14,7 +14,10 @@ RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_MRC_CACHE(PRESERVE) 8K + UNIFIED_MRC_CACHE 16K { + RECOVERY_MRC_CACHE(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + } RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d4796a2..9358890 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -74,14 +74,6 @@ } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { - /* - * Don't store training data if we're in recovery mode - * because we always want to retrain due to - * possibility of RW training data possibly being - * updated to a different format. - */ - if (vboot_recovery_mode_enabled()) - return; assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION, (const void *)te->blob_address, te->size)); @@ -138,20 +130,12 @@ /* output area, QCLib fills in DDR details */ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); - /* - * We never want to use training data when booting into - * recovery mode. - */ - if (vboot_recovery_mode_enabled()) { + /* Attempt to load DDR Training Blob */ + data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, + _ddr_training, REGION_SIZE(ddr_training)); + if (data_size < 0) { + printk(BIOS_ERR, "Unable to load previous training data.\n"); memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } else { - /* Attempt to load DDR Training Blob */ - data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, - _ddr_training, REGION_SIZE(ddr_training)); - if (data_size < 0) { - printk(BIOS_ERR, "Unable to load previous training data.\n"); - memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } } qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index c66dc92..db819ad 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select CACHE_MRC_SETTINGS + select HAS_RECOVERY_MRC_CACHE select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 -- To view, visit https://review.coreboot.org/c/coreboot/+/46651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e Gerrit-Change-Number: 46651 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020