Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 )
Change subject: soc/intel: drop unneeded ISST configuration code
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Looks good to me. But maybe wait a little for other
people to chime in.
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@16
PS6, Line 16: OS to not enable HWP if that is desired.
> I confirmed this on CML-U (Clevo L141CU), KBL-H (Smc X11SSM-F) and SKL-U (Acer ES1-572) by printing […]
Done
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46319 )
Change subject: Makefile.inc: Omit unsupported warnings with non-GCC compilers
......................................................................
Makefile.inc: Omit unsupported warnings with non-GCC compilers
Clang does not support some of these warning options, and does not
accept comments to indicate intentional fall-through in case statements.
Do not enable them for non-GCC compilers for now. Note that this patch
does not change any warnings when using the official coreboot toolchain.
TEST=Use system Clang 10.0.1 (x86_64) to build for Asrock B85M Pro4.
The resulting coreboot image is able to boot and suspend/resume.
Change-Id: I4df3f89af6dac8ae65fb104a21547d5ac358221b
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Makefile.inc
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46319/1
diff --git a/Makefile.inc b/Makefile.inc
index 882673b..373e312 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -425,12 +425,13 @@
CFLAGS_common += -pipe -g -nostdinc -std=gnu11
CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
-CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
-CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
-CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else
+CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
+CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
ifeq ($(CONFIG_COMPILER_GCC),y)
+# Clang does not support some warning options, and does not accept fallthrough comments
+CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wimplicit-fallthrough
# Don't add these GCC specific flags when running scan-build
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46653 )
Change subject: Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"
......................................................................
Patch Set 2: Code-Review+2
> Patch Set 2: Code-Review+2
>
> Build error isn't your fault (something to do with xeon_xp & tiogapass...) I'd try to rebase these on master
Rebase on CB:46662 instead
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36278 )
Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
......................................................................
Patch Set 102:
Executables have no place in our repo: you never know what the host environment is that a board is built on (besides the obvious licensing issue.)
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46653 )
Change subject: Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"
......................................................................
Patch Set 2: Code-Review+2
Build error isn't your fault (something to do with xeon_xp & tiogapass...) I'd try to rebase these on master
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46652 )
Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded…
File src/mainboard/google/dedede/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46652/2/src/mainboard/google/deded…
PS2, Line 42: <soc/intel/common/acpi/lpit.asl>
Do we lose any functionality in the kernel by not exposing LPIT? We won't really use any function now that the save/restore is being dropped. But, does the kernel use the table to make any decision about S0ix?
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