coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: mediatek: Add SPI tick_dly setting
by Mengqi Zhang (Code Review) 21 Jun '19

21 Jun '19

Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32461 Change subject: mediatek: Add SPI tick_dly setting ...................................................................... mediatek: Add SPI tick_dly setting Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32461/1 diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 9d6c38b..1efbc7a 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -18,6 +18,8 @@ void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, + 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, + 0); } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 1193bb3..7eee080 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -34,6 +34,6 @@ gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3c50389..89169ef 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -89,7 +89,8 @@ if (CONFIG(OAK_HAS_TPM2)) gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz, + 0); setup_chromeos_gpios(); diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 162db59..81a9098 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -84,8 +84,9 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select); -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks); +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly); void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz); + unsigned int speed_hz, unsigned int tick_dly); #endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 71ed95a..1af6f10 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -53,7 +53,7 @@ } void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz) + unsigned int speed_hz, unsigned int tick_dly) { u32 div, sck_ticks, cs_ticks; @@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n", bus, pad_select, SPI_HZ / (sck_ticks * 2)); - mtk_spi_set_timing(regs, sck_ticks, cs_ticks); + mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly); clrsetbits_le32(&regs->spi_cmd_reg, (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index aaef3aa..525f160 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -43,4 +43,10 @@ SPI_CFG0_CS_SETUP_SHIFT = 24, }; +enum { + SPI_CFG1_TICK_DLY_SHIFT = 30, + + SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, +}; + #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 0cc8377..d009441 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -38,14 +38,17 @@ gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(&regs->spi_cfg0_reg, ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 9bc7121..dd63e91 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -49,5 +49,11 @@ SPI_CFG2_SCK_HIGH_SHIFT = 16, }; +enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, + +}; #endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index a79dafb..c57e60f 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -109,7 +109,8 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(&regs->spi_cfg0_reg, ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | @@ -119,6 +120,8 @@ ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK, + tick_dly << SPI_CFG1_TICK_DLY_SHIFT); clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Gerrit-Change-Number: 32461 Gerrit-PatchSet: 1 Gerrit-Owner: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: mediatek/mt8183: Add SPI GPIO driving setting
by Mengqi Zhang (Code Review) 21 Jun '19

21 Jun '19

Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32460 Change subject: mediatek/mt8183: Add SPI GPIO driving setting ...................................................................... mediatek/mt8183: Add SPI GPIO driving setting Set SPI GPIO driving to support SPI FLASH. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I95002ec71abd751c33c089185db04ed4a8686699 Signed-off-by: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> --- M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/gpio.h M src/soc/mediatek/mt8183/mt8183.c 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32460/1 diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 327d389..2bff3d0 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -20,6 +20,7 @@ EN_OFFSET = 0x60, SEL_OFFSET = 0x80, EH_RSEL_OFFSET = 0xF0, + SPI_GPIO_DRV_OFFSET = 0xA0, }; static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, @@ -128,3 +129,14 @@ I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5), I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5)); } + +enum { + SPI_GPIO_DRV_MASK = 0xf, +}; + +void gpio_set_spi_driving(void) +{ + clrsetbits_le32((void *)IOCFG_LM_BASE + SPI_GPIO_DRV_OFFSET, + SPI_GPIO_DRV_MASK, 0x4); +} + diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index 5a98953..e446853 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -617,5 +617,6 @@ static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); void gpio_set_i2c_eh_rsel(void); +void gpio_set_spi_driving(void); #endif diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index c441980..7ceeb90 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@ #include <soc/mt8183.h> #include <soc/wdt.h> +#include <soc/gpio.h> void mt8183_early_init(void) { mtk_wdt_init(); + gpio_set_spi_driving(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95002ec71abd751c33c089185db04ed4a8686699 Gerrit-Change-Number: 32460 Gerrit-PatchSet: 1 Gerrit-Owner: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> Gerrit-MessageType: newchange

5 30

Change in ...coreboot[master]: google/kukui: Enable RTC
by You-Cheng Syu (Code Review) 21 Jun '19

21 Jun '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33356 Change subject: google/kukui: Enable RTC ...................................................................... google/kukui: Enable RTC Enable RTC so that we can see correct timestamp in CrOS eventlogs. BUG=b:134461866 TEST='mosys eventlog list' shows correct timestamp on Kukui Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16 --- M src/mainboard/google/kukui/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33356/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 6831d1e..7719506 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select RTC select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/33356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16 Gerrit-Change-Number: 33356 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mediatek/mt8183: Support RTC in ramstage
by You-Cheng Syu (Code Review) 21 Jun '19

21 Jun '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33355 Change subject: mediatek/mt8183: Support RTC in ramstage ...................................................................... mediatek/mt8183: Support RTC in ramstage We need to support RTC in ramstage so that we can see correct timestamp in ChromiumOS eventlog. BUG=b:134461866 TEST='mosys eventlog list' shows correct timestamp on Kukui Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b --- M src/soc/mediatek/mt8183/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33355/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5392a9e..d35a07e 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -45,6 +45,8 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/pmic_wrap.c +ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b Gerrit-Change-Number: 33355 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: mt8183: add efuse calibration in auxadc
by JG Poxu (Code Review) 21 Jun '19

21 Jun '19

JG Poxu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32800 Change subject: mt8183: add efuse calibration in auxadc ...................................................................... mt8183: add efuse calibration in auxadc due to not get efuse calibration, auxadc get value has deviated Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52 Signed-off-by: jg_poxu <jg_poxu(a)mediatek.com> --- M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/efuse.h 3 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32800/1 diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c old mode 100644 new mode 100755 index a167d2b..408f911 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -18,11 +18,43 @@ #include <delay.h> #include <soc/addressmap.h> #include <soc/auxadc.h> +#include <soc/efuse.h> #include <soc/infracfg.h> #include <timer.h> static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; +/* For calibration EFUSE: + * 1. ADC_GE_A[9:0] *(0x11F101B4)[19:10] Default:512 + * 2. ADC_OE_A[9:0] *(0x11F101B4)[9:0] Default:512 + * 3. ADC_CALI_EN_A(1b) *(0x11F101B4)[20] + */ +#define ADC_GE_A_SHIFT 10 +#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT) +#define ADC_OE_A_SHIFT 0 +#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT) +#define ADC_CALI_EN_A_SHIFT 20 +#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT) +#define AUXADC_CALI_INIT ~((uint32_t)1) +static int cali_oe = AUXADC_CALI_INIT; +static int cali_ge = AUXADC_CALI_INIT; + +static void mt_auxadc_update_cali(void) +{ + int cali_reg; + int cali_ge_a; + int cali_oe_a; + + cali_reg = read32(&mtk_efuse->adc_cali_reg); + + if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) { + cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT; + cali_ge_a = ((cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT); + /*In sw implement guide, ge should div 4096. But we don't do that now due to it will multi 4096 later*/ + cali_ge = cali_ge_a - 512; + cali_oe = cali_oe_a - 512; + } +} static uint32_t auxadc_get_rawdata(int channel) { setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); @@ -47,5 +79,8 @@ assert(channel < 16); /* 1.5V in 4096 steps */ - return (int)((int64_t)auxadc_get_rawdata(channel) * 1500000 / 4096); + rawvalue = auxadc_get_rawdata(channel); + + rawvalue = rawvalue - cali_oe; + return (int)((int64_t)rawvalue * 1500000 / (4096 + cali_ge)); } diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h old mode 100644 new mode 100755 index d41b2b9..e9f80d1 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -50,6 +50,7 @@ IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000, + EFUSEC_BASE = IO_PHYS + 0x01F10000, IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, diff --git a/src/soc/mediatek/mt8183/include/soc/efuse.h b/src/soc/mediatek/mt8183/include/soc/efuse.h new file mode 100644 index 0000000..2705497 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/efuse.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <stdint.h> + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52 Gerrit-Change-Number: 32800 Gerrit-PatchSet: 1 Gerrit-Owner: JG Poxu <jg_poxu(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

7 31

Change in ...coreboot[master]: google/kukui: Revise FMAP firmware layout
by Hung-Te Lin (Code Review) 21 Jun '19

21 Jun '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33239 Change subject: google/kukui: Revise FMAP firmware layout ...................................................................... google/kukui: Revise FMAP firmware layout Adjust FMAP sections that - ELOG only needs 4K (by driver limitation) - SHARED_DATA only needs 4K or less (for netboot params) - SMMSTORE is probably not needed since UEFI@ARM is not available yet - VPD can be smaller (most x86 has only 8K) - Increase RW_LEGACY to 1M (recommended value) - Move all new saved space to RW CBFS BUG=b:134624821 TEST=Built Kukui image and boots on Rev2 units. Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/chromeos.fmd 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33239/1 diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 23e5576..f43774a 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -9,22 +9,22 @@ } RO_VPD(PRESERVE)@0x1f0000 0x10000 } - RW_SECTION_A@0x200000 0x78000 { + RW_SECTION_A@0x200000 0x7c000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x75f00 - RW_FWID_A@0x77f00 0x100 + FW_MAIN_A(CBFS) 0x79f00 + RW_FWID_A 0x100 } - RW_SHARED@0x278000 0x2000 { - SHARED_DATA@0x0 0x2000 + RW_SHARED@0x27c000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 - RW_SECTION_B@0x280000 0x78000 { + RW_NVRAM(PRESERVE)@0x27d000 0x2000 + # ELOG driver has hard-coded the size to 4k. + RW_ELOG(PRESERVE)@0x27f000 0x1000 + RW_SECTION_B@0x280000 0x7c000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x75f00 - RW_FWID_B@0x77f00 0x100 + FW_MAIN_B(CBFS) 0x79f00 + RW_FWID_B 0x100 } - RW_VPD(PRESERVE)@0x2f8000 0x8000 - SMMSTORE(PRESERVE)@0x300000 0x20000 - RW_LEGACY(CBFS)@0x320000 0xe0000 + RW_VPD(PRESERVE)@0x2fc000 0x4000 + RW_LEGACY(CBFS)@0x300000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/33239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1 Gerrit-Change-Number: 33239 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: cpu/amd/family_10h-family_15h: Fix 'if' condition identical branches
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33257 Change subject: cpu/amd/family_10h-family_15h: Fix 'if' condition identical branches ...................................................................... cpu/amd/family_10h-family_15h: Fix 'if' condition identical branches Change-Id: I1c937a62388c38090ee2cc3228973cfb8361bac7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33257/1 diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index d6a4725..f416d9c 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -504,10 +504,9 @@ if (is_fam15h()) { /* core 1 on node 0 is special; to avoid corrupting the * BSP do not alter MTRRs on that core */ + fam15_bsp_core1_apicid = 1; if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1; - else - fam15_bsp_core1_apicid = 1; + fam15_bsp_core1_apicid += CONFIG_APIC_ID_OFFSET; if (apicid == fam15_bsp_core1_apicid) set_mtrrs = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c937a62388c38090ee2cc3228973cfb8361bac7 Gerrit-Change-Number: 33257 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: cbfstool: Drop update-fit option
by Patrick Rudolph (Code Review) 21 Jun '19

21 Jun '19

Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Subrata Banik, Duncan Laurie, build bot (Jenkins), Kai Michaelis, Patrick Georgi, Furquan Shaikh, Amol N Sukerkar, Roy Wen, Christian Walter, David Hendricks, Philipp Deppenwiese, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31496 to look at the new patch set (#13). Change subject: cbfstool: Drop update-fit option ...................................................................... cbfstool: Drop update-fit option The ifittool is used instead. Drop old code. Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/Kconfig M util/cbfstool/Makefile.inc M util/cbfstool/cbfstool.c M util/cbfstool/fit.c M util/cbfstool/fit.h 5 files changed, 1 insertion(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31496/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/31496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Gerrit-Change-Number: 31496 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: cbfstool: Add ifittool
by Patrick Rudolph (Code Review) 21 Jun '19

21 Jun '19

Hello Aaron Durbin, Julius Werner, Subrata Banik, Duncan Laurie, build bot (Jenkins), Kai Michaelis, Patrick Georgi, Furquan Shaikh, Amol N Sukerkar, Roy Wen, David Hendricks, Philipp Deppenwiese, Nico Huber, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31493 to look at the new patch set (#14). Change subject: cbfstool: Add ifittool ...................................................................... cbfstool: Add ifittool Add the IntelFirmwareInterfaceTable-tool to modify the FIT. As cbfstool is overloaded with arguments, introduce a new tool to only modify FIT, which brings it's own command line syntax. Provide clean interface to: * Clear FIT * Add entry to CBFS file * Add entry to REGION * Delete entries * Add support for types other than 1 * Add support to dump current table * Add support for top-swap * Sort entries by type Most code is reused from existing cbfstool and functionality of cbfstool is kept. It will be removed once the make system uses only ifittool. Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout" and https://github.com/slimbootloader/slimbootloader . Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/cbfstool/Makefile M util/cbfstool/Makefile.inc M util/cbfstool/fit.c M util/cbfstool/fit.h A util/cbfstool/ifittool.c 5 files changed, 1,121 insertions(+), 140 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31493/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/31493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Gerrit-Change-Number: 31493 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/google/snappy: Remove unneeded 'else'
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33335 Change subject: mb/google/snappy: Remove unneeded 'else' ...................................................................... mb/google/snappy: Remove unneeded 'else' 'else' is not needed after a 'break' or 'return'. Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/reef/variants/snappy/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33335/1 diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index 950a029..b34b8e2c 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -70,8 +70,8 @@ if ((ch < '0') || (ch > '9')) { vpd_sku_num = -1; break; - } else - vpd_sku_num = vpd_sku_num * 10 + (ch - '0'); + } + vpd_sku_num = vpd_sku_num * 10 + (ch - '0'); } if (vpd_sku_num != -1) -- To view, visit https://review.coreboot.org/c/coreboot/+/33335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772 Gerrit-Change-Number: 33335 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019