coreboot-gerrit June 2019

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Change in ...coreboot[master]: Add support for Hygon Dhyana processor
by Name of user not set (Code Review) 21 Jun '19

21 Jun '19

Name of user not set #1002411 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32876 Change subject: Add support for Hygon Dhyana processor ...................................................................... Add support for Hygon Dhyana processor src/arch/x86/cpu.c: Add hygon vendor string verify. Background: Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between AMD and Haiguang Information Technology Co.,Ltd., aims at providing high performance x86 processor for China server market. Its first generation processor codename is Dhyana, which originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series number(Family 18h). More details can be found on: http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.153858328… Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f Signed-off-by: Jinke Fan <fanjinke(a)hygon.cn> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32876/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index e6c9435..cfab219 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -113,6 +113,7 @@ { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, { X86_VENDOR_NSC, "Geode by NSC", }, { X86_VENDOR_SIS, "SiS SiS SiS ", }, + { X86_VENDOR_HYGON, "HygonGenuine", }, }; static const char *const x86_vendor_name[] = { @@ -126,6 +127,7 @@ [X86_VENDOR_TRANSMETA] = "Transmeta", [X86_VENDOR_NSC] = "NSC", [X86_VENDOR_SIS] = "SiS", + [X86_VENDOR_HYGON] = "Hygon", }; static const char *cpu_vendor_name(int vendor) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 078ea17..ff1a33b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -152,6 +152,7 @@ #define X86_VENDOR_TRANSMETA 8 #define X86_VENDOR_NSC 9 #define X86_VENDOR_SIS 10 +#define X86_VENDOR_HYGON 11 #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -- To view, visit https://review.coreboot.org/c/coreboot/+/32876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f Gerrit-Change-Number: 32876 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002411 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/nvidia/ck804/lpc.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33063 Change subject: sb/nvidia/ck804/lpc.c: Remove variable set but not used ...................................................................... sb/nvidia/ck804/lpc.c: Remove variable set but not used Change-Id: I19b16bc2052440ca191cf3e30810ddc58a485a60 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/ck804/lpc.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33063/1 diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2123554..8caa8ed 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -124,10 +124,9 @@ get_option(&on, "slow_cpu"); if (on) { u16 pm10_bar; - u32 dword; pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); + inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); -- To view, visit https://review.coreboot.org/c/coreboot/+/33063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b16bc2052440ca191cf3e30810ddc58a485a60 Gerrit-Change-Number: 33063 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/amd/amdfam10/northbridge.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33013 Change subject: nb/amd/amdfam10/northbridge.c: Remove variable set but not used ...................................................................... nb/amd/amdfam10/northbridge.c: Remove variable set but not used Change-Id: I62a51b794dedcf320b8054125e75aa041035ce33 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/northbridge.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33013/1 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1d071c1..db40267 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1690,7 +1690,6 @@ uint8_t fam15h = 0; uint8_t rev_gte_d = 0; - unsigned nb_cfg_54; uint32_t family; uint32_t model; @@ -1700,7 +1699,6 @@ if (is_fam15h()) { /* Family 15h or later */ fam15h = 1; - nb_cfg_54 = 1; } if ((model >= 0x8) || fam15h) @@ -1862,7 +1860,6 @@ uint8_t compute_unit_count = 0; uint32_t f3xe8; - uint8_t dual_node = 0; for (i = 0; i < sysconf.nodes; i++) { struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); @@ -1871,10 +1868,6 @@ f3xe8 = pci_read_config32(f3x_dev, 0xe8); - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - /* Determine the number of active compute units on this node */ f5x80 = pci_read_config32(f5x_dev, 0x80); cu_enabled = f5x80 & 0xf; -- To view, visit https://review.coreboot.org/c/coreboot/+/33013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a51b794dedcf320b8054125e75aa041035ce33 Gerrit-Change-Number: 33013 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem/raminit.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32944 Change subject: nb/intel/nehalem/raminit.c: Remove variable set but not used ...................................................................... nb/intel/nehalem/raminit.c: Remove variable set but not used Change-Id: I216d4d00375fcff9e740583b9e17013e0495360c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 12 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32944/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 5b6077f..e54350c 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3740,11 +3740,6 @@ u16 deven; int cbmem_wasnot_inited; - /* only used for dummy reads */ - volatile u8 tmp8; - volatile u16 tmp16; - volatile u32 tmp32; - x2ca8 = MCHBAR8(0x2ca8); deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); @@ -4058,10 +4053,10 @@ pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); - tmp8 = MCHBAR8(0x1150); - tmp8 = MCHBAR8(0x1151); - tmp8 = MCHBAR8(0x1022); - tmp8 = MCHBAR8(0x16d0); + MCHBAR8(0x1150); + MCHBAR8(0x1151); + MCHBAR8(0x1022); + MCHBAR8(0x16d0); MCHBAR32(0x1300) = 0x60606060; MCHBAR32(0x1304) = 0x60606060; MCHBAR32(0x1308) = 0x78797a7b; @@ -4249,10 +4244,10 @@ } MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! - tmp32 = MCHBAR32(0x1c04); // !!!! + MCHBAR32(0x1c04); // !!!! MCHBAR32(0x1804) = 0x406080; - tmp8 = MCHBAR8(0x2ca8); + MCHBAR8(0x2ca8); if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); @@ -4264,9 +4259,9 @@ MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); - tmp16 = MCHBAR16(0x2c20); // !!!! - tmp16 = MCHBAR16(0x2c10); // !!!! - tmp16 = MCHBAR16(0x2c00); // !!!! + MCHBAR16(0x2c20); // !!!! + MCHBAR16(0x2c10); // !!!! + MCHBAR16(0x2c00); // !!!! MCHBAR16(0x2c00) = 0x8c0; udelay(1000); write_1d0(0, 0x33d, 0, 0); @@ -4372,7 +4367,7 @@ MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! - tmp8 = MCHBAR8(0x1f0); // !!!! + MCHBAR8(0x1f0); // !!!! program_board_delay(&info); @@ -4431,7 +4426,7 @@ info.populated_ranks[channel][0][0] ? 9 : 1); rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! - tmp32 = MCHBAR32(0x144); // !!!! + MCHBAR32(0x144); // !!!! write_1d0(2, 0xae, 6, 1); write_1d0(2, 0x300, 6, 1); write_1d0(2, 0x121, 3, 1); @@ -4681,7 +4676,7 @@ reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK - tmp8 = MCHBAR8(0xe08); // = 0x0 + MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 MCHBAR8_OR(0x1210, 2); MCHBAR32(0x1200) = 0x8800440; -- To view, visit https://review.coreboot.org/c/coreboot/+/32944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I216d4d00375fcff9e740583b9e17013e0495360c Gerrit-Change-Number: 32944 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32943 Change subject: sb/intel/bd82x6x/early_pch.c: Remove variable set but not used ...................................................................... sb/intel/bd82x6x/early_pch.c: Remove variable set but not used Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32943/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..883a4aa 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -40,7 +40,6 @@ static u32 read_iobp(u32 address) { - volatile u32 tmp; u32 ret; RCBA32(IOBPIRI) = address; @@ -48,14 +47,13 @@ wait_iobp(); ret = RCBA32(IOBPD); wait_iobp(); - tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? return ret; } static void write_iobp(u32 address, u32 val) { - volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ @@ -67,7 +65,7 @@ wait_iobp(); RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? } void early_pch_init_native_dmi_pre(void) @@ -84,14 +82,12 @@ void early_pch_init_native_dmi_post(void) { - volatile u32 tmp; - - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x01200654; - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x012a0654; - tmp = RCBA32(0x0050); // !!! = 0x012a0654 - tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA32(0x0050); // !!! = 0x012a0654 + RCBA8(0x1114); // !!! = 0x00 RCBA8(0x1114) = 0x05; /* @@ -118,7 +114,7 @@ */ RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); /* Read back register */ - tmp = RCBA32(0x2020); + RCBA32(0x2020); /* Virtual Channel private Resource Control Register. * Enable channel. @@ -127,7 +123,7 @@ */ RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); /* Read back register */ - tmp = RCBA32(0x2030); + RCBA32(0x2030); /* Virtual Channel ME Resource Control Register. * Enable channel. @@ -139,7 +135,7 @@ /* Lock Virtual Channel Resource control register. */ RCBA32(0x0050) |= 0x80000000; /* Read back register */ - tmp = RCBA32(0x0050); + RCBA32(0x0050); /* Wait for virtual channels negotiation pending */ while (RCBA16(0x201a) & VCNEGPND) @@ -155,24 +151,23 @@ void early_pch_init_native (void) { - volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); RCBA32(0x2088) = 0x00109000; - tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac); // !!! = 0x00000000 RCBA32(0x20ac) = 0x40000000; RCBA32(0x100c) = 0x01110000; RCBA8(0x2340) = 0x1b; - tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314); // !!! = 0x0a080000 RCBA32(0x2314) = 0x0a280000; - tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310); // !!! = 0xc809605b RCBA32(0x2310) = 0xa809605b; RCBA32(0x2324) = 0x00854c74; - tmp = RCBA8(0x0400); // !!! = 0x00 - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA8(0x0400); // !!! = 0x00 + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; write_iobp(0xea007f62, 0x00590133); -- To view, visit https://review.coreboot.org/c/coreboot/+/32943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Gerrit-Change-Number: 32943 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem/raminit.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33004 Change subject: nb/intel/nehalem/raminit.c: Remove variable set but not used ...................................................................... nb/intel/nehalem/raminit.c: Remove variable set but not used Change-Id: I5d3a04970fa57f07ca7dd748f114ac0cd6955522 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 3 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33004/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 5b6077f..59a4ea3 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -2235,26 +2235,11 @@ u8 lower_usable[8]; u8 upper_usable[8]; unsigned short num_successfully_checked[8]; - u8 secondary_total_rank; u8 reg1b3; + int i; - if (info->populated_ranks_mask[1]) { - if (channel == 1) - secondary_total_rank = - info->populated_ranks[1][0][0] + - info->populated_ranks[1][0][1] - + info->populated_ranks[1][1][0] + - info->populated_ranks[1][1][1]; - else - secondary_total_rank = 0; - } else - secondary_total_rank = total_rank; - - { - int i; - for (i = 0; i < 8; i++) - state[i] = BEFORE_USABLE; - } + for (i = 0; i < 8; i++) + state[i] = BEFORE_USABLE; if (!first_run) { int is_all_ok = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/33004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d3a04970fa57f07ca7dd748f114ac0cd6955522 Gerrit-Change-Number: 33004 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33548 Change subject: sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree ...................................................................... sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/devicetree.cb M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c M util/autoport/bd82x6x.go 42 files changed, 37 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/33548/1 diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index 68556d9..a729049 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); } diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 6d0b3af..6c3d980 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -33,12 +33,6 @@ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); - /* Map 1 byte to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0x00164d); - - /* Map a range for the runtime_port registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - #if CONFIG(DRIVERS_UART_8250IO) /* Enable COM1 */ if (sio1007_enable_uart_at(SIO_PORT)) { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 67bcbcb..b35a8b4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -30,7 +30,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d34b1e4..844f754 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -33,13 +33,6 @@ /* EC Decode Range Port60/64 and Port62/66 */ /* Enable EC and PS/2 Keyboard/Mouse*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); - - /* EC Decode Range Port68/6C */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001); - - /* EC Decode Range Port 380-387 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001); - } void mainboard_rcba_config(void) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 8da1308..2f3f07c 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -34,28 +34,12 @@ void pch_enable_lpc(void) { - const struct device *lpc; - const struct southbridge_intel_bd82x6x_config *config = NULL; - - lpc = pcidev_on_root(0x1f, 0); - if (!lpc) - return; - if (lpc->chip_info) - config = lpc->chip_info; - if (!config) - return; - /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ GAMEL_LPC_EN | COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } void mainboard_rcba_config(void) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 76a4b4b..ac06fbc 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -31,12 +31,6 @@ /* Parrot EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); - - /* Map EC_IO decode to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001); - - /* Map EC registers 68/6C decode to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001); } void mainboard_rcba_config(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7539dd7..6690c68 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -41,9 +41,6 @@ */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | FDD_LPC_EN); - - /* Stout EC Decode Range Port68/6C */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 585d61d..79a84b7 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -46,6 +46,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 21e3cea..6401909 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -28,8 +28,6 @@ */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 515d20f..a301857 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -55,6 +55,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index 68af61b..ba6f956 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -27,8 +27,6 @@ */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 79259b4..a06aea9 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -54,6 +54,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index a3fb5f0..f30c3a8 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -34,8 +34,6 @@ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 2a115cc..4715372 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -55,6 +55,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index a876173..b1375e8 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -33,8 +33,6 @@ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index 7d74c94..d98402c 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -43,6 +43,7 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index a7f6b22..8956b08 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -34,8 +34,6 @@ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 5d4e5b8..d626934 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -46,6 +46,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index db3296c..8ff7813 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -30,8 +30,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 4d0d639..ad69ca2 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -46,6 +46,7 @@ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index f62024c..5f8df63 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -33,8 +33,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 60072b0..4ed1f3c 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -44,8 +44,11 @@ register "sata_port_map" = "0x3f" + register "gen1_dec" = "0x00fc1601" + # runtime_port registers + register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen3_dec" = "0x003c0701" register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9a9fc24..a28ae78 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,12 +39,6 @@ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); - /* Map 256 bytes at 0x1600 to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); - - /* Map a range for the runtime_port registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - /* Enable COM1 */ if (sio1007_enable_uart_at(SIO_PORT)) { pci_write_config16(dev, LPC_EN, diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index c8003ae..426ac4e 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -29,10 +29,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 03ee4db..9114100 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -31,9 +31,6 @@ void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Memory map KB9012 EC registers */ diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 806c72a..ebf5aed 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -56,10 +56,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index c42d165..27c77a7 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -57,10 +57,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index db50bb3..1f4b90d 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -55,9 +55,6 @@ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, - (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 4edd5c6..e590bb6 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -26,10 +26,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 96d07fe..d431f27 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -59,10 +59,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 2b850a2..7d2a7d3 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -59,10 +59,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index ea550aa..79a2276 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -26,11 +26,6 @@ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index c65060f..acbe1ab 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -36,10 +36,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index a5b0c81..066f4c7 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -35,10 +35,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index f97c3f5..fe6992a 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -32,10 +32,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 7199473..feae5bf 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -61,6 +61,7 @@ # EC range is 0xa00-0xa3f register "gen1_dec" = "0x003c0a01" register "gen2_dec" = "0x003c0b01" + register "gen3_dec" = "0x00fc1601" register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index a77149d..d4b6dd8 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -43,9 +43,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - /* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); - try_enabling_LPC47N207_uart(); #else /* Enable SuperIO + EC + KBC */ diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 192e63d..060fc40 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -50,6 +50,7 @@ register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x00fc1601" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a8e28d6..77fd160 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -55,9 +55,6 @@ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); - /* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); - try_enabling_LPC47N207_uart(); #else /* Enable SuperIO + PS/2 Keyboard/Mouse */ diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 296e896..0f18ef3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -25,10 +25,6 @@ void pch_enable_lpc(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..0082c91 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,10 +258,31 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } +static void pch_enable_lpc_gen_decode(void) +{ + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_bd82x6x_config *config = NULL; + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + void early_pch_init(void) { pch_enable_lpc(); + pch_enable_lpc_gen_decode(); + pch_enable_bars(); pch_generic_setup(); diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index e93704e..141ec5c 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -28,7 +28,7 @@ } for i := uint(0); i < max; i++ { - if ((constraint>>i)&1 == 1) { + if (constraint>>i)&1 == 1 { fmt.Fprintf(sb, " .gpio%d = %s,\n", (set-1)*32+i, bits[partno][(val>>i)&1]) @@ -236,8 +236,8 @@ "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), "c2_latency": FormatHexLE16(FADT[96:98]), "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), - "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), - "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)), + "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), + "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), }, PCISlots: []PCISlot{ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, @@ -315,10 +315,6 @@ { `) RestorePCI16Simple(sb, addr, 0x82) - RestorePCI32Simple(sb, addr, 0x84) - RestorePCI32Simple(sb, addr, 0x88) - RestorePCI32Simple(sb, addr, 0x8c) - RestorePCI32Simple(sb, addr, 0x90) RestorePCI16Simple(sb, addr, 0x80) -- To view, visit https://review.coreboot.org/c/coreboot/+/33548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Gerrit-Change-Number: 33548 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33575 Change subject: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE ...................................................................... soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE What it really means to do is to use different FSP headers. Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33575/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..7b4282c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,7 +3,7 @@ help Intel Cannonlake support -config SOC_INTEL_COMMON_CANNONLAKE_BASE +config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS bool default n select SOC_INTEL_CANNONLAKE @@ -11,7 +11,7 @@ Single Kconfig option to select common base Cannonlake support. This Kconfig will help to select majority of CNL SoC features. Major difference that exist today between - SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig + SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig are in FSP Header Files. Hence this Kconfig might help to select required SoC support FSP headers. Any future Intel SoC would like to make use of CNL support might just select this Kconfig. @@ -19,21 +19,21 @@ config SOC_INTEL_COFFEELAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Coffeelake support config SOC_INTEL_WHISKEYLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Whiskeylake support config SOC_INTEL_COMETLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..3b4c980 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -111,7 +111,7 @@ enum { SaGv_Disabled, SaGv_FixedLow, -#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index d98e2f5..7dae615 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -500,7 +500,7 @@ * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)) return 0; /* diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 77bad8f..a1e3d76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -69,7 +69,7 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Gerrit-Change-Number: 33575 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at...
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33015 Change subject: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35 ...................................................................... cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35 Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33015/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 3dfdd8d..4ebbe18 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -34,7 +34,7 @@ /* Haswell bus clock is fixed at 100MHz */ #define HASWELL_BCLK 100 -#define CORE_THREAD_COUNT_MSR 0x35 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 25cf243..95d719c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -732,7 +732,7 @@ int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f4c5d93..c0d2434 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,7 +22,7 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define CORE_THREAD_COUNT_MSR 0x35 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 524e49c..80d85f3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -513,7 +513,7 @@ int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/33015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Gerrit-Change-Number: 33015 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place
by HAOUAS Elyes (Code Review) 21 Jun '19

21 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31193 Change subject: cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place ...................................................................... cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31193/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31c921d..733205a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -37,6 +37,8 @@ #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_MISC_ENABLE 0x1a0 +#define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define SPEED_STEP_ENABLE_BIT (1 << 16) #define IA32_ENERGY_PERF_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1b27eef..0d469c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -96,10 +96,6 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) - /* Read BCLK from MSR */ unsigned int bus_freq_khz(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/31193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Gerrit-Change-Number: 31193 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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