coreboot-gerrit June 2019

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Change in ...coreboot[master]: arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readability
by Felix Held (Code Review) 21 Jun '19

21 Jun '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33628 Change subject: arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readability ...................................................................... arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readability ALIGN_UP is an alias for ALIGN. Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/smbios.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33628/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 54c2b09..50dac7f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1150,12 +1150,12 @@ int max_struct_size = 0; int handle = 0; - current = ALIGN(current, 16); + current = ALIGN_UP(current, 16); printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current); se = (struct smbios_entry *)current; current += sizeof(struct smbios_entry); - current = ALIGN(current, 16); + current = ALIGN_UP(current, 16); tables = current; update_max(len, max_struct_size, smbios_write_type0(&current, -- To view, visit https://review.coreboot.org/c/coreboot/+/33628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc Gerrit-Change-Number: 33628 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201: Remove duplicated include
by Peter Lemenkov (Code Review) 21 Jun '19

21 Jun '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33626 Change subject: mb/lenovo/x201: Remove duplicated include ...................................................................... mb/lenovo/x201: Remove duplicated include Change-Id: I0917f11091b8c93c21c0e25690440b7dd0e9c8ba Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/mainboard.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/33626/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 0e20afe..a26adcb 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -26,7 +26,6 @@ #include "dock.h" #include <drivers/intel/gma/int15.h> #include <cpu/x86/lapic.h> -#include <device/pci_ops.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0917f11091b8c93c21c0e25690440b7dd0e9c8ba Gerrit-Change-Number: 33626 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/facebook/fbg1701: Remove unused Kconfig symbols
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33562 Change subject: mb/facebook/fbg1701: Remove unused Kconfig symbols ...................................................................... mb/facebook/fbg1701: Remove unused Kconfig symbols Change-Id: Ifc61fd11c9d7a4d192eaae73c5421f643d27d817 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33562/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 3f45194..b3c589d 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -78,14 +78,6 @@ bool default n -config BOOTBLOCK_LOC - hex - default 0xFFFF0000 - -config BOOTBLOCK_SIZE - hex - default 0x10000 - config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/33562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc61fd11c9d7a4d192eaae73c5421f643d27d817 Gerrit-Change-Number: 33562 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/nuvoton/nct6791d: Add symbol to select COM port
by Felix Held (Code Review) 21 Jun '19

21 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33640 ) Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/33640/1/src/superio/nuvoton/common/early_se… File src/superio/nuvoton/common/early_serial.c: https://review.coreboot.org/#/c/33640/1/src/superio/nuvoton/common/early_se… PS1, Line 74: pnp_write_config(dev, 0x2a, 0x00); > I thought so, but has anybody initialized the superio at such an early stage? the other bits aren't […] yeah, it probably shouldn't matter too much here. If I saw that correctly, compared to the default values also only the bits related to the serial port get changed, so it should be ok in the current state. -- To view, visit https://review.coreboot.org/c/coreboot/+/33640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62dc18810026f9b1550da19950f66af605600ec8 Gerrit-Change-Number: 33640 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Jun 2019 11:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h110m: Correct Kconfig symbol selection
by Maxim Polyakov (Code Review) 21 Jun '19

21 Jun '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33439 ) Change subject: mb/asrock/h110m: Correct Kconfig symbol selection ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a Gerrit-Change-Number: 33439 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Jun 2019 10:42:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/nuvoton/nct6791d: Add symbol to select COM port
by Maxim Polyakov (Code Review) 21 Jun '19

21 Jun '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33640 ) Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port ...................................................................... Patch Set 1: Code-Review+1 early console works well on the Asrock-H110M-DVS board -- To view, visit https://review.coreboot.org/c/coreboot/+/33640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62dc18810026f9b1550da19950f66af605600ec8 Gerrit-Change-Number: 33640 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <m.poliakov(a)yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Jun 2019 10:42:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: add support for SAMSUNG EMCP DDR
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32243 Change subject: mediatek/mt8183: add support for SAMSUNG EMCP DDR ...................................................................... mediatek/mt8183: add support for SAMSUNG EMCP DDR BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 4 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c old mode 100644 new mode 100755 index cbfb08d..ca74fa7 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -21,6 +21,7 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc old mode 100644 new mode 100755 index 1e11140..d685b1a --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,6 +1,7 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c new file mode 100755 index 0000000..1e0c362 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x1, 0x1}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x58, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c old mode 100644 new mode 100755 index 11a46bb..1fefd34 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -32,7 +32,7 @@ enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -10, + FIRST_DQS_DELAY = -16, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Gerrit-Change-Number: 32243 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: fix mode register setting fail issue
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32284 Change subject: mediatek/mt8183: fix mode register setting fail issue ...................................................................... mediatek/mt8183: fix mode register setting fail issue the mode register setting of DRAM maybe failed without delay operate, need add delay after each MR write. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I51785e90b2014994be5018bfe543245d44626242 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c 1 file changed, 128 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32284/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c old mode 100644 new mode 100755 index d275127..98108c6 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -18,6 +18,7 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> #include <soc/infracfg.h> +#include <delay.h> struct reg_init_value { u32 *addr; @@ -620,7 +621,52 @@ {&ch[1].phy.shu[0].rk[1].b[1].dq[1], 0x22000000}, {&ch[1].phy.shu[0].b[0].dll[1], 0x00022501}, - /* dramc mode register init */ + /* update the ac timing */ + {&ch[0].ao.shu[0].actim[0], 0x06020c07}, + {&ch[0].ao.shu[0].actim[1], 0x10080501}, + {&ch[0].ao.shu[0].actim[2], 0x07070201}, + {&ch[0].ao.shu[0].actim[3], 0x6164002c}, + {&ch[0].ao.shu[0].actim[4], 0x22650077}, + {&ch[0].ao.shu[0].actim[5], 0x0a000c0b}, + {&ch[0].ao.shu[0].actim_xrt, 0x05030609}, + {&ch[0].ao.shu[0].ac_time_05t, 0x000106e1}, + {&ch[0].ao.catraining1, 0x0b000000}, + {&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004}, + {&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004}, + {&ch[0].ao.shu[0].odtctrl, 0xc001004f}, + {&ch[0].ao.shu[0].conf[1], 0x34000d0f}, + {&ch[0].ao.shu[0].conf[2], 0x9007640f}, + {&ch[0].ao.shu[0].scintv, 0x4e39eb36}, + {&ch[0].ao.shu[0].ckectrl, 0x33210000}, + {&ch[0].ao.ckectrl, 0x88d02440}, + {&ch[0].ao.shu[0].rankctl, 0x64300003}, + {&ch[0].ao.shu[0].rankctl, 0x64301203}, + {&ch[1].ao.shu[0].actim[0], 0x06020c07}, + {&ch[1].ao.shu[0].actim[1], 0x10080501}, + {&ch[1].ao.shu[0].actim[2], 0x07070201}, + {&ch[1].ao.shu[0].actim[3], 0x6164002c}, + {&ch[1].ao.shu[0].actim[4], 0x22650077}, + {&ch[1].ao.shu[0].actim[5], 0x0a000c0b}, + {&ch[1].ao.shu[0].actim_xrt, 0x05030609}, + {&ch[1].ao.shu[0].ac_time_05t, 0x000106e1}, + {&ch[1].ao.catraining1, 0x0b000000}, + {&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004}, + {&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004}, + {&ch[1].ao.shu[0].odtctrl, 0xc001004f}, + {&ch[1].ao.shu[0].conf[1], 0x34000d0f}, + {&ch[1].ao.shu[0].conf[2], 0x9007640f}, + {&ch[1].ao.shu[0].scintv, 0x4e39eb36}, + {&ch[1].ao.shu[0].ckectrl, 0x33210000}, + {&ch[1].ao.ckectrl, 0x88d02440}, + {&ch[1].ao.shu[0].rankctl, 0x64300003}, + {&ch[1].ao.shu[0].rankctl, 0x64301203}, + {&ch[0].ao.arbctl, 0x00000c80}, + {&ch[0].ao.rstmask, 0x00000000}, + {&ch[0].ao.arbctl, 0x00000c80}, +}; + +struct reg_init_value dramc_mode_reg_init_sequence[] = { + /* dramc power on sequence */ {&ch[0].phy.misc_ctrl1, 0x8100908c}, {&ch[1].phy.misc_ctrl1, 0x8100908c}, {&ch[0].ao.ckectrl, 0x88d02480}, @@ -632,6 +678,8 @@ {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[1].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000000}, + + /* CH0 dramc ZQ Calibration */ {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000000}, @@ -641,70 +689,104 @@ {&ch[0].ao.mrs, 0x00000000}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000d18}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x00000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x00000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0000020b}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x00000b00}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x00001638}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x00000e5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000d58}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x00000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x00000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0000022d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x00000b23}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x00001634}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x00000e10}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* dramc ZQ Calibration */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, @@ -715,76 +797,112 @@ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000d18}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x01000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x01000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0100020b}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x01000b00}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x01001638}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x01000e5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000d58}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR12 */ {&ch[0].ao.mrs, 0x01000c5d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR1 */ {&ch[0].ao.mrs, 0x01000156}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR2 */ {&ch[0].ao.mrs, 0x0100022d}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR11 */ {&ch[0].ao.mrs, 0x01000b23}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR22 */ {&ch[0].ao.mrs, 0x01001634}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR14 */ {&ch[0].ao.mrs, 0x01000e10}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR3 */ {&ch[0].ao.mrs, 0x01000330}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x00000330}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x00000dd8}, {&ch[0].ao.spcmd, 0x00000001}, {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, + + /* MR13 */ {&ch[0].ao.mrs, 0x01000dd8}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x01000dd8}, @@ -792,9 +910,12 @@ {&ch[0].ao.spcmd, 0x00000000}, {&ch[0].ao.ckectrl, 0x88d02440}, {&ch[0].ao.mrs, 0x01000dd8}, + {&ch[0].ao.shu[0].hwset_mr13, 0x00d8000d}, {&ch[0].ao.shu[0].hwset_vrcg, 0x00d8000d}, {&ch[0].ao.shu[0].hwset_mr2, 0x002d0002}, + + /* CH1 dramc ZQ Calibration */ {&ch[1].ao.mrs, 0x00000000}, {&ch[1].ao.dramc_pd_ctrl, 0xc4000107}, {&ch[1].ao.ckectrl, 0x88d02440}, @@ -961,49 +1082,6 @@ {&ch[1].ao.shu[0].hwset_mr2, 0x002d0002}, {&ch[0].ao.mrs, 0x00000dd8}, {&ch[1].ao.mrs, 0x00000dd8}, - - /* update the ac timing */ - {&ch[0].ao.shu[0].actim[0], 0x06020c07}, - {&ch[0].ao.shu[0].actim[1], 0x10080501}, - {&ch[0].ao.shu[0].actim[2], 0x07070201}, - {&ch[0].ao.shu[0].actim[3], 0x6164002c}, - {&ch[0].ao.shu[0].actim[4], 0x22650077}, - {&ch[0].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[0].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[0].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[0].ao.catraining1, 0x0b000000}, - {&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[0].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[0].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[0].ao.shu[0].conf[2], 0x9007640f}, - {&ch[0].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[0].ao.shu[0].ckectrl, 0x33210000}, - {&ch[0].ao.ckectrl, 0x88d02440}, - {&ch[0].ao.shu[0].rankctl, 0x64300003}, - {&ch[0].ao.shu[0].rankctl, 0x64301203}, - {&ch[1].ao.shu[0].actim[0], 0x06020c07}, - {&ch[1].ao.shu[0].actim[1], 0x10080501}, - {&ch[1].ao.shu[0].actim[2], 0x07070201}, - {&ch[1].ao.shu[0].actim[3], 0x6164002c}, - {&ch[1].ao.shu[0].actim[4], 0x22650077}, - {&ch[1].ao.shu[0].actim[5], 0x0a000c0b}, - {&ch[1].ao.shu[0].actim_xrt, 0x05030609}, - {&ch[1].ao.shu[0].ac_time_05t, 0x000106e1}, - {&ch[1].ao.catraining1, 0x0b000000}, - {&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004}, - {&ch[1].ao.shu[0].odtctrl, 0xc001004f}, - {&ch[1].ao.shu[0].conf[1], 0x34000d0f}, - {&ch[1].ao.shu[0].conf[2], 0x9007640f}, - {&ch[1].ao.shu[0].scintv, 0x4e39eb36}, - {&ch[1].ao.shu[0].ckectrl, 0x33210000}, - {&ch[1].ao.ckectrl, 0x88d02440}, - {&ch[1].ao.shu[0].rankctl, 0x64300003}, - {&ch[1].ao.shu[0].rankctl, 0x64301203}, - {&ch[0].ao.arbctl, 0x00000c80}, - {&ch[0].ao.rstmask, 0x00000000}, - {&ch[0].ao.arbctl, 0x00000c80}, }; void dramc_init(void) @@ -1011,4 +1089,10 @@ for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++) write32(dramc_init_sequence[i].addr, dramc_init_sequence[i].value); + + for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) { + write32(dramc_mode_reg_init_sequence[i].addr, + dramc_mode_reg_init_sequence[i].value); + udelay(2); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51785e90b2014994be5018bfe543245d44626242 Gerrit-Change-Number: 32284 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: mediatek/mt8183: enable DDR low power feature
by huayang duan (Code Review) 21 Jun '19

21 Jun '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32010 Change subject: mediatek/mt8183: enable DDR low power feature ...................................................................... mediatek/mt8183: enable DDR low power feature BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/emi.h 6 files changed, 132 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32010/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 3ca5c22..15771ee 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -154,9 +154,6 @@ for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { - /* Track rising and update rising/falling together */ - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], - 0x1 << 29); clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), @@ -172,8 +169,6 @@ (0x3 << 18) | (0x3 << 16)); } - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); - /* Rx DLY tracking setting (Static) */ clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), @@ -181,6 +176,7 @@ clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); for (u8 b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[9], @@ -201,10 +197,12 @@ static void dramc_hw_dqs_gating_tracking(u8 chn) { - setbits_le32(&ch[chn].ao.stbcal, (0x3 << 26) | (0x1 << 0)); + clrsetbits_le32(&ch[chn].ao.stbcal, + (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4), + (0x3 << 26) | (0x1 << 0)); clrsetbits_le32(&ch[chn].ao.stbcal1, (0xffff << 16) | (0x1 << 8) | (0x1 << 6), - (0x1 << 16) | (0x1 << 8) | (0x0 << 6)); + (0x1 << 16) | (0x1 << 8) | (0x1 << 6)); clrsetbits_le32(&ch[chn].phy.misc_ctrl0, (0x1 << 24) | (0x1f << 11) | (0xf << 0), @@ -262,6 +260,72 @@ dramc_set_broadcast(broadcast_bak); } + +static void DramcDummyReadForTrackingEnable(u8 chn) +{ + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16); + + for (size_t r = 0; r < 2; r++) + for (size_t i = 0; i < 4; i++) + write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i], + 0xaaaa5555); + + clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + for (size_t r = 0; r < 2; r++) { + clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, + (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), + (0x7fff << 0) | (0x3f0 << 17)); + setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + } + + clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); +} + +static void SetCKE2RankIndependent(u8 chn) +{ + clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); + clrsetbits_le32(&ch[chn].ao.ckectrl, + (0x1 << 1) | (0xf << 8) | (0x7 << 13), + (0x4 << 8) | (0x2 << 13)); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits_le32(&ch[chn].ao.shu[shu].conf[2], + (0x1 << 29) | (0x1 << 31)); + clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9); +} + +static void dramc_pa_improve(u8 chn) +{ + clrbits_le32(&ch[chn].ao.clkar, 0xffff); + clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); +} + +static void dramc_set_mr13_vrcg_to_Normal(u8 chn) +{ + for (u8 rank = 0; rank < RANK_MAX; rank++) + dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + + for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); +} + +static void dramc_enable_dramc_dcm(void) +{ + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + (0x7 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits_le32(&ch[chn].ao.clkar, 0x1 << 31); + } +} + void dramc_runtime_config(void) { clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); @@ -270,39 +334,83 @@ transfer_pll_to_spm_control(); setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25); + dramc_show("%s with: broadcast %d\n", __func__, dramc_get_broadcast()); + + + /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) dramc_rx_input_delay_tracking(chn); + /* HW_GATING: ON */ dramc_hw_gating_init(); dramc_hw_gating_onoff(CHANNEL_A, true); + dramc_hw_gating_onoff(CHANNEL_B, true); + /* HW_GATING DBG: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) clrbits_le32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); + /* DUMMY_READ_FOR_TRACKING: ON */ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + DramcDummyReadForTrackingEnable(chn); + + /* ZQCS_ENABLE_LP4: ON */ clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30); + /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ dramc_phy_low_power_enable(); dramc_enable_phy_dcm(true); + /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); + /* SPM_CONTROL_AFTERK: ON */ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff); write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef); write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef); + /* IMPEDANCE_TRACKING: ON */ dramc_impedance_tracking_enable(); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + /* TEMP_SENSOR: ON */ clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28); setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); - clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 18); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + + /* PER_BANK_REFRESH: ON */ + clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + + /* HW_SAVE_FOR_SR: ON */ + clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); + setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0); + clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); + + /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */ + SetCKE2RankIndependent(chn); + + /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */ + clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); + clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19); + + /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */ + dramc_pa_improve(chn); + + /* DRAM DRS DISABLE */ + clrsetbits_le32(&ch[chn].ao.drsctrl, + (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), + (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | + (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26); + + dramc_set_mr13_vrcg_to_Normal(chn); } + + enable_emi_dcm(); + dramc_enable_dramc_dcm(); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f3c76a9..11a46bb 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -127,7 +127,7 @@ setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); } -static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 757a453..b7d7d7b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -292,6 +292,15 @@ emi_init2(params); } +void enable_emi_dcm(void) +{ + clrsetbits_le32(&emi_regs->conm, 0xff << 24, 0x0 << 24); + clrsetbits_le32(&emi_regs->conn, 0xff << 24, 0x0 << 24); + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].emi.chn_conb, 0xff << 24, 0x0 << 24); +} + static void do_calib(const struct sdram_params *params) { dramc_apply_pre_calibration_config(); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 781443a..7e0f34e 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -127,4 +127,6 @@ void dramc_calibrate_all_channels(const struct sdram_params *params); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); +void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value); + #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 2487504..f0720a7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -265,10 +265,7 @@ struct dramc_ao_regs_rk { uint32_t dqsosc; uint32_t rsvd_1[5]; - uint32_t dummy_rd_wdata0; - uint32_t dummy_rd_wdata1; - uint32_t dummy_rd_wdata2; - uint32_t dummy_rd_wdata3; + uint32_t dummy_rd_wdata[4]; uint32_t dummy_rd_adr; uint32_t dummy_rd_bk; uint32_t pre_tdqsck[12]; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 81e3d91..2c04a50 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -38,6 +38,7 @@ int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); +void enable_emi_dcm(void); void mt_set_emi(const struct sdram_params *params); void mt_mem_init(const struct sdram_params *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/32010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Gerrit-Change-Number: 32010 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

8 20

Change in ...coreboot[master]: Documentatioan: update stage handoff protocol
by Xiang Wang (Code Review) 21 Jun '19

21 Jun '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33460 Change subject: Documentatioan: update stage handoff protocol ...................................................................... Documentatioan: update stage handoff protocol Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M Documentation/arch/riscv/index.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33460/1 diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 888651d..9a5de34 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -15,7 +15,7 @@ will have been done. These payloads rely on the SBI and can not replace it. ## Stage handoff protocol -On entry to a stage or payload, +On entry to a stage or payload (including SELF payloads), * all harts are running. * A0 is the hart ID. * A1 is the pointer to the Flattened Device Tree (FDT). -- To view, visit https://review.coreboot.org/c/coreboot/+/33460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3 Gerrit-Change-Number: 33460 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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