coreboot-gerrit June 2019

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Change in ...coreboot[master]: src/cpu: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32821 Change subject: src/cpu: Use 'include <stdlib.h>' when appropriate ...................................................................... src/cpu: Use 'include <stdlib.h>' when appropriate Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/allwinner/a10/clock.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/uart.c M src/cpu/x86/mtrr/mtrr.c 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32821/1 diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index 76198b7..9e4e93d 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <delay.h> #include <lib.h> -#include <stdlib.h> static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 5d653d1..cca0049 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -16,7 +16,6 @@ #ifndef INIT_CPUS_H #define INIT_CPUS_H -#include <stdlib.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index cc2d1a4..16e54d7 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 5b85601..724e09c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 30b00bb..98ce555 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 2685839..8660f2c 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <cpu/ti/am335x/gpio.h> #include <stdint.h> -#include <stdlib.h> static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio, uint32_t *bit) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index c482a85..4e9d012 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <types.h> #include <console/uart.h> #include <device/mmio.h> diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d87c3d4..91ff14a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -22,7 +22,6 @@ */ #include <stddef.h> -#include <stdlib.h> #include <string.h> #include <bootstate.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Gerrit-Change-Number: 32821 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...vboot[master]: vboot: Move 'static' to the beginning of declaration
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/33675 Change subject: vboot: Move 'static' to the beginning of declaration ...................................................................... vboot: Move 'static' to the beginning of declaration Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Change-Id: Ia05289a2eafb55be760ecce5fc2bce69eead0aa3 --- M cgpt/cgpt_common.c M firmware/2lib/2misc.c M firmware/lib/cgptlib/cgptlib_internal.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/75/33675/1 diff --git a/cgpt/cgpt_common.c b/cgpt/cgpt_common.c index c129d92..b4cd041 100644 --- a/cgpt/cgpt_common.c +++ b/cgpt/cgpt_common.c @@ -675,7 +675,7 @@ const Guid guid_efi = GPT_ENT_TYPE_EFI; const Guid guid_unused = GPT_ENT_TYPE_UNUSED; -const static struct { +static const struct { const Guid *type; char *name; char *description; diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 8b6a19f..ecea5ec 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -15,7 +15,7 @@ #include "2rsa.h" int vb2_validate_gbb_signature(uint8_t *sig) { - const static uint8_t sig_xor[VB2_GBB_SIGNATURE_SIZE] = + static const uint8_t sig_xor[VB2_GBB_SIGNATURE_SIZE] = VB2_GBB_XOR_SIGNATURE; int i; for (i = 0; i < VB2_GBB_SIGNATURE_SIZE; i++) { diff --git a/firmware/lib/cgptlib/cgptlib_internal.c b/firmware/lib/cgptlib/cgptlib_internal.c index 77a0de2..e74ab89 100644 --- a/firmware/lib/cgptlib/cgptlib_internal.c +++ b/firmware/lib/cgptlib/cgptlib_internal.c @@ -12,7 +12,7 @@ #include "gpt_misc.h" #include "utility.h" -const static int MIN_SECTOR_SIZE = 512; +static const int MIN_SECTOR_SIZE = 512; size_t CalculateEntriesSectors(GptHeader* h, uint32_t sector_bytes) { -- To view, visit https://review.coreboot.org/c/vboot/+/33675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Ia05289a2eafb55be760ecce5fc2bce69eead0aa3 Gerrit-Change-Number: 33675 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nuvoton/early_serial: improve comments on serial pinmux settings
by Felix Held (Code Review) 22 Jun '19

22 Jun '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33665 Change subject: nuvoton/early_serial: improve comments on serial pinmux settings ...................................................................... nuvoton/early_serial: improve comments on serial pinmux settings Change-Id: I36c0d752df97810bd99d2eec27403545421ce533 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/nuvoton/common/early_serial.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33665/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 7f22993..eaa3c5a 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -66,11 +66,11 @@ nuvoton_pnp_enter_conf_state(dev); if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) - /* Route GPIO8 pin group to COM A */ + /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x40); if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A)) - /* Route GPIO8 pin group to COM A */ + /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x00); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/33665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c0d752df97810bd99d2eec27403545421ce533 Gerrit-Change-Number: 33665 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in ...chrome-ec[master]: 3rdparty/chromeec: Move 'static' to the beginning of declaration
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/chrome-ec/+/33677 Change subject: 3rdparty/chromeec: Move 'static' to the beginning of declaration ...................................................................... 3rdparty/chromeec: Move 'static' to the beginning of declaration Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Change-Id: I97e476167bfa5c44d3c296ecfb4b7f1ff292f0df --- M board/nami/led.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/chrome-ec refs/changes/77/33677/1 diff --git a/board/nami/led.c b/board/nami/led.c index 70d4b0f..a68f2f7 100644 --- a/board/nami/led.c +++ b/board/nami/led.c @@ -102,7 +102,7 @@ * Discharge in S5 Off * Battery Error Amber on 1sec off 1sec */ -const static led_patterns battery_pattern_0 = { +static const led_patterns battery_pattern_0 = { /* discharging: s0, s3, s5 */ {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(20)}, {LED_OFF, PULSE_NO}}, /* charging: s0, s3, s5 */ @@ -119,7 +119,7 @@ * Battery Error Blinking white (0.5 sec On and 0.5 sec Off) * fuel < 10% Blinking white (1 sec On, 1 sec Off) */ -const static led_patterns battery_pattern_1 = { +static const led_patterns battery_pattern_1 = { /* discharging: s0, s3, s5 */ {{LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}}, /* charging: s0, s3, s5 */ @@ -134,7 +134,7 @@ * System S3 1 second on, 1 second off * System S4/S5 Off */ -const static led_patterns power_pattern_1 = { +static const led_patterns power_pattern_1 = { /* discharging: s0, s3, s5 */ {{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}}, /* charging: s0, s3, s5 */ @@ -149,7 +149,7 @@ * Connected to AC power / Charging(1% -99%) Amber (solid on) * Not connected to AC power Off */ -const static led_patterns battery_pattern_2 = { +static const led_patterns battery_pattern_2 = { /* discharging: s0, s3, s5 */ {{LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}}, /* charging: s0, s3, s5 */ @@ -164,7 +164,7 @@ * S3/Lid closed: White Pulsing (Gradual 1sec on, Gradual 1sec off, 2sec off) * S5: Off */ -const static led_patterns power_pattern_2 = { +static const led_patterns power_pattern_2 = { /* discharging: s0, s3, s5 */ {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(20)}, {LED_OFF, PULSE_NO}}, /* charging: s0, s3, s5 */ @@ -182,7 +182,7 @@ * Discharge in S5: Off * Battery Error: Amber on 1sec off 1sec */ -const static led_patterns battery_pattern_3 = { +static const led_patterns battery_pattern_3 = { /* discharging: s0, s3, s5 */ {{LED_WHITE, 0}, {LED_AMBER, ALTERNATE(BLINK(10))}, {LED_OFF, 0}}, /* charging: s0, s3, s5 */ -- To view, visit https://review.coreboot.org/c/chrome-ec/+/33677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: chrome-ec Gerrit-Branch: master Gerrit-Change-Id: I97e476167bfa5c44d3c296ecfb4b7f1ff292f0df Gerrit-Change-Number: 33677 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...arm-trusted-firmware[master]: arm-trusted-firmware: Move 'static' to the beginning of declaration
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/arm-trusted-firmware/+/33676 Change subject: arm-trusted-firmware: Move 'static' to the beginning of declaration ...................................................................... arm-trusted-firmware: Move 'static' to the beginning of declaration Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Change-Id: Ifcd716b5b714fac9647537901cdd40147bdefa11 --- M plat/nvidia/tegra/soc/t186/plat_memctrl.c M plat/xilinx/zynqmp/zynqmp_ipi.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/arm-trusted-firmware refs/changes/76/33676/1 diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index 957ecf1..6a7f036 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -10,7 +10,7 @@ /******************************************************************************* * Array to hold stream_id override config register offsets ******************************************************************************/ -const static uint32_t tegra186_streamid_override_regs[] = { +static const uint32_t tegra186_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_PTCR, MC_STREAMID_OVERRIDE_CFG_AFIR, MC_STREAMID_OVERRIDE_CFG_HDAR, @@ -88,7 +88,7 @@ /******************************************************************************* * Array to hold the security configs for stream IDs ******************************************************************************/ -const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { +static const mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE), @@ -166,7 +166,7 @@ /******************************************************************************* * Array to hold the transaction override configs ******************************************************************************/ -const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = { +static const mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = { mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), diff --git a/plat/xilinx/zynqmp/zynqmp_ipi.c b/plat/xilinx/zynqmp/zynqmp_ipi.c index 755a3b7..77d7a69 100644 --- a/plat/xilinx/zynqmp/zynqmp_ipi.c +++ b/plat/xilinx/zynqmp/zynqmp_ipi.c @@ -55,7 +55,7 @@ }; /* Zynqmp ipi configuration table */ -const static struct zynqmp_ipi_config zynqmp_ipi_table[] = { +static const struct zynqmp_ipi_config zynqmp_ipi_table[] = { /* APU IPI */ { .ipi_bit_mask = 0x1, -- To view, visit https://review.coreboot.org/c/arm-trusted-firmware/+/33676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: arm-trusted-firmware Gerrit-Branch: master Gerrit-Change-Id: Ifcd716b5b714fac9647537901cdd40147bdefa11 Gerrit-Change-Number: 33676 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers: Add missing #include <commonlib/helpers.h>
by HAOUAS Elyes (Code Review) 22 Jun '19

22 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33659 Change subject: drivers: Add missing #include <commonlib/helpers.h> ...................................................................... drivers: Add missing #include <commonlib/helpers.h> ALIGN and ALIGN_UP needs 'helpers.h Change-Id: Ia18f69b58bae6d841d800dc38745ff27f51cec46 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/smmstore/store.c 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33659/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 1fbb553..fcb353c 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -14,6 +14,7 @@ #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 67ed099..bd3f478 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,6 +15,7 @@ #include <arch/symbols.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <fsp/car.h> diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2702b5a..ab9f28f 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -16,6 +16,7 @@ #include <bootstate.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <console/streams.h> #include <fsp/util.h> diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index eff011a..803492f 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -17,6 +17,7 @@ #include <arch/acpi.h> #include <cbmem.h> #include <cf9_reset.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <fsp/memmap.h> #include <fsp/romstage.h> diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 6f2014b..833407d 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -16,6 +16,7 @@ #include <boot_device.h> #include <cbfs.h> #include <fmap.h> +#include <commonlib/helpers.h> #include <commonlib/region.h> #include <console/console.h> #include <smmstore.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18f69b58bae6d841d800dc38745ff27f51cec46 Gerrit-Change-Number: 33659 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard: Add Clevo W650SZ
by Iru Cai (vimacs) (Code Review) 22 Jun '19

22 Jun '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33325 to review the following change. Change subject: mainboard: Add Clevo W650SZ ...................................................................... mainboard: Add Clevo W650SZ This port is based on the code generated with autoport with Haswell support (30890). This laptop has two flash chips with 2MB(ME)+4MB(BIOS), so it depends on 30980. Now it can boot Arch Linux from a USB flash disk with SeaBIOS payload. The EHCI debug port is at the right hand side of the laptop, but the debug message stops to display after mrc.bin initializes USB. Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/w650sz/Kconfig A src/mainboard/clevo/w650sz/Kconfig.name A src/mainboard/clevo/w650sz/Makefile.inc A src/mainboard/clevo/w650sz/acpi/ec.asl A src/mainboard/clevo/w650sz/acpi/platform.asl A src/mainboard/clevo/w650sz/acpi/superio.asl A src/mainboard/clevo/w650sz/acpi_tables.c A src/mainboard/clevo/w650sz/board_info.txt A src/mainboard/clevo/w650sz/devicetree.cb A src/mainboard/clevo/w650sz/dsdt.asl A src/mainboard/clevo/w650sz/gma-mainboard.ads A src/mainboard/clevo/w650sz/gpio.c A src/mainboard/clevo/w650sz/hda_verb.c A src/mainboard/clevo/w650sz/mainboard.c A src/mainboard/clevo/w650sz/romstage.c 17 files changed, 728 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33325/1 diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig new file mode 100644 index 0000000..9aacf38 --- /dev/null +++ b/src/mainboard/clevo/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_CLEVO + +choice + prompt "Mainboard model" + +source "src/mainboard/clevo/*/Kconfig.name" + +endchoice + +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Clevo" + +endif diff --git a/src/mainboard/clevo/Kconfig.name b/src/mainboard/clevo/Kconfig.name new file mode 100644 index 0000000..2e72ffa --- /dev/null +++ b/src/mainboard/clevo/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_NOTEBOOK + bool "Clevo" diff --git a/src/mainboard/clevo/w650sz/Kconfig b/src/mainboard/clevo/w650sz/Kconfig new file mode 100644 index 0000000..61b740c --- /dev/null +++ b/src/mainboard/clevo/w650sz/Kconfig @@ -0,0 +1,50 @@ +if BOARD_NOTEBOOK_W650SZ + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_6144 + select CPU_INTEL_HASWELL + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default notebook/w650sz + +config MAINBOARD_PART_NUMBER + string + default "W650SZ" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x655 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif diff --git a/src/mainboard/clevo/w650sz/Kconfig.name b/src/mainboard/clevo/w650sz/Kconfig.name new file mode 100644 index 0000000..f2ec7e4 --- /dev/null +++ b/src/mainboard/clevo/w650sz/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_NOTEBOOK_W650SZ + bool "W650SZ" diff --git a/src/mainboard/clevo/w650sz/Makefile.inc b/src/mainboard/clevo/w650sz/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/clevo/w650sz/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/clevo/w650sz/acpi/ec.asl b/src/mainboard/clevo/w650sz/acpi/ec.asl new file mode 100644 index 0000000..f2f4269 --- /dev/null +++ b/src/mainboard/clevo/w650sz/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/clevo/w650sz/acpi/platform.asl b/src/mainboard/clevo/w650sz/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/clevo/w650sz/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/clevo/w650sz/acpi/superio.asl b/src/mainboard/clevo/w650sz/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/clevo/w650sz/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/clevo/w650sz/acpi_tables.c b/src/mainboard/clevo/w650sz/acpi_tables.c new file mode 100644 index 0000000..5dc98d8 --- /dev/null +++ b/src/mainboard/clevo/w650sz/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/clevo/w650sz/board_info.txt b/src/mainboard/clevo/w650sz/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/clevo/w650sz/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/clevo/w650sz/devicetree.cb b/src/mainboard/clevo/w650sz/devicetree.cb new file mode 100644 index 0000000..223253e --- /dev/null +++ b/src/mainboard/clevo/w650sz/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x041e041e" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x041e041e" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0069" + register "gen2_dec" = "0x000c3321" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpi7_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x85" + register "pirqh_routing" = "0x84" + register "sata_ahci" = "1" + register "sata_port_map" = "0x25" + device pci 14.0 on # xHCI Controller + subsystemid 0x1558 0x0655 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1558 0x0655 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1558 0x0655 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1558 0x0655 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1558 0x0655 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1558 0x0655 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x1558 0x0655 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1558 0x0655 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1558 0x0655 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1558 0x0655 + end + device pci 1f.3 on # SMBus + subsystemid 0x1558 0x0655 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1558 0x0655 + end + device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + subsystemid 0x1558 0x0655 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1558 0x0655 + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x1558 0x0655 + end + end +end diff --git a/src/mainboard/clevo/w650sz/dsdt.asl b/src/mainboard/clevo/w650sz/dsdt.asl new file mode 100644 index 0000000..f3ed3d2 --- /dev/null +++ b/src/mainboard/clevo/w650sz/dsdt.asl @@ -0,0 +1,29 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/clevo/w650sz/gma-mainboard.ads b/src/mainboard/clevo/w650sz/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/clevo/w650sz/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/w650sz/gpio.c b/src/mainboard/clevo/w650sz/gpio.c new file mode 100644 index 0000000..5bcc83e --- /dev/null +++ b/src/mainboard/clevo/w650sz/gpio.c @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio46 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/clevo/w650sz/hda_verb.c b/src/mainboard/clevo/w650sz/hda_verb.c new file mode 100644 index 0000000..0230a69 --- /dev/null +++ b/src/mainboard/clevo/w650sz/hda_verb.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862807, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000002, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x80860101), + + /* NID 0x03. */ + AZALIA_PIN_CFG(0x0, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/w650sz/mainboard.c b/src/mainboard/clevo/w650sz/mainboard.c new file mode 100644 index 0000000..aee0269 --- /dev/null +++ b/src/mainboard/clevo/w650sz/mainboard.c @@ -0,0 +1,23 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/clevo/w650sz/romstage.c b/src/mainboard/clevo/w650sz/romstage.c new file mode 100644 index 0000000..7a0011e --- /dev/null +++ b/src/mainboard/clevo/w650sz/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* Mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0, 0xa4, 0 }, + .ec_present = 0, + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + .bist = bist, + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923 Gerrit-Change-Number: 33325 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in ...coreboot[master]: soc/intel/common: Add SMBIOS type 131 fields
by Francois Toguo Fotso (Code Review) 21 Jun '19

21 Jun '19

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33067 Change subject: soc/intel/common: Add SMBIOS type 131 fields ...................................................................... soc/intel/common: Add SMBIOS type 131 fields Fill SMBIOS type 131 for intel SOCs. BUG=none TEST=Boot to OS and check with dmidecode that entry is added. Change-Id: Ida4e1a95e20289fbab01e773c18e00ce74aa8223 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 692 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33067/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6de..3aaf817 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -17,6 +17,7 @@ #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> #include <delay.h> #include <device/pci.h> @@ -25,6 +26,7 @@ #include <intelblocks/cse.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <smbios.h> #include <string.h> #include <timer.h> @@ -68,6 +70,37 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) +#define MKHI_GROUP_ID_GEN 0xff +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_GROUP_ID_PTFTYPE 0x03 +#define MKHI_PTFTYPE_GET_RULE 0x02 +#define MKHI_GROUP_ID_FW_STATE 0x03 +#define MKHI_FW_STATE_GET_RULE 0x02 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_GET_PLATFORM_TYPE 0x02 +#define MEI_HOST_ADDRESS 0 +#define MEI_ADDRESS_MKHI 0x07 +#define TXT_IN_VMX_AND_SMX_MSR 0xFF03 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0x0 +#define PCI_FN_PCH_LAN 6 +#define SMBIOS_INTEL_TYPE131 0x83 +#define BITS_0_THROUGH_2_MASK 0x7 +#define BITS_3_THROUGH_7_MASK 0x38 +#define WORD_0_MASK 0x0000ffff +#define WORD_1_MASK 0xffff0000 + +union mkhi_header { + uint32_t data; + struct { + uint32_t group_id: 8; + uint32_t command: 7; + uint32_t is_response: 1; + uint32_t reserved: 8; + uint32_t result: 8; + } __packed fields; +}; struct cse_device { uintptr_t sec_bar; @@ -491,8 +524,489 @@ return 0; } +/* Get ME firmware version */ +int mkhi_get_fw_version(me_fw_version *version) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + } __packed msg; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fw_version version_info; + } __packed rsp; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; + msg.mkhi_hdr.fields.command = MKHI_GET_FW_VERSION; + msg.mkhi_hdr.fields.is_response = 0; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME version.\n"); + return 0; + } + + memcpy(version, &rsp.version_info, sizeof(rsp.version_info)); + + return 1; +} + + +/* Get ME Firmware Capabilities */ +int mkhi_get_fwcaps(me_fwcaps *f_cap) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_FWCAPS; + msg.mkhi_hdr.fields.command = MKHI_FWCAPS_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fwcaps fwcaps; + } __packed rsp; + rsp.fwcaps.id = 0; + rsp.fwcaps.length = 0x4; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME FW CAPS.\n"); + return 0; + } + + memcpy(f_cap, &rsp.fwcaps, sizeof(rsp.fwcaps)); + + return 1; +} + +/* Get ME Firmware configuration state */ +int mkhi_get_fw_fea_state(mefwcaps_sku *f_cap) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_FW_STATE; + msg.mkhi_hdr.fields.command = MKHI_FW_STATE_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0x20; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + me_fwcaps fwcaps; + } __packed rsp; + rsp.fwcaps.id = 0; + rsp.fwcaps.length = 0x4; + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get ME FW CAPS CONFIG.\n"); + return 0; + } + + memcpy(f_cap, &rsp.fwcaps.caps_sku, sizeof(rsp.fwcaps.caps_sku)); + + return 1; +} + +int mkhi_get_platform_type(me_platform_type *platf_type) +{ + int res; + size_t reply_size; + + struct fw_version_cmd { + union mkhi_header mkhi_hdr; + u32 rule_id; + } __packed msg; + + msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_PTFTYPE; + msg.mkhi_hdr.fields.command = MKHI_PTFTYPE_GET_RULE; + msg.mkhi_hdr.fields.is_response = 0; + msg.rule_id = 0x1d; + + struct fw_version_response { + union mkhi_header mkhi_hdr; + uint32_t id; + uint8_t length; + me_platform_type platf_type; + } __packed rsp; + rsp.id = 0; + rsp.length = sizeof(union mkhi_header) + sizeof(me_platform_type); + + res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + + if (!res) { + printk(BIOS_ERR, "Failed to send HECI message.\n"); + return 0; + } + + reply_size = sizeof(rsp); + res = heci_receive(&rsp, &reply_size); + + if (!res) { + printk(BIOS_ERR, "Failed to receive HECI reply.\n"); + return 0; + } + + if (rsp.mkhi_hdr.fields.result != 0) { + printk(BIOS_ERR, "Failed to get PLATFORM TTYPE .\n"); + return 0; + } + + memcpy(platf_type, &rsp.platf_type, sizeof(rsp.platf_type)); + + return 1; +} + +void get_me_cpu_capab(cpu_cap *cpu_capabilities) +{ + msr_t msr; + u32 feature_flag = cpuid(1).ecx; + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (feature_flag & CPUID_SMX) + cpu_capabilities->lt_txt_cap = 1; + else + cpu_capabilities->lt_txt_cap = 0; + + if ((msr.lo & TXT_IN_VMX_AND_SMX_MSR) == TXT_IN_VMX_AND_SMX_MSR) + cpu_capabilities->lt_txt_enabled = 1; + else + cpu_capabilities->lt_txt_enabled = 0; + + if (feature_flag & CPUID_VMX) + cpu_capabilities->vtx_cap = 1; + else + cpu_capabilities->vtx_cap = 0; + + if (msr.lo & (1 << 2)) + cpu_capabilities->vtx_enabled = 1; + else + cpu_capabilities->vtx_enabled = 0; + + return; +} + +/* + * MEBX is a UEFI Option ROM for the ME. + * Missing without the UEFI payload. All 0s for coreboot + */ +void get_mebx_version(mebx_ver *mebx_version ) +{ + mebx_version->major = 0; + mebx_version->minor = 0; + mebx_version->hotfix = 0; + mebx_version->build = 0; + + return; +} + +void get_pch_capab(pch_cap *pch_capabilities) +{ + pch_capabilities->function_number = PCI_FUNC(PCH_DEVFN_LPC); + pch_capabilities->device_number = PCH_DEV_SLOT_LPC; + pch_capabilities->bus_number = DEFAULT_PCI_BUS_NUMBER_PCH; + pch_capabilities->device_id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + return; +} + + +void get_me_platf_capab(me_cap *platf_cap) +{ + + me_fw_version version; + if (mkhi_get_fw_version(&version)) + { + platf_cap->me_major_ver = version.code_major; + platf_cap->me_minor_ver = version.code_minor; + platf_cap->me_build_ver = version.code_build_number; + platf_cap->me_hotfix_ver = version.code_hot_fix; + } else { + platf_cap->me_major_ver = 0; + platf_cap->me_minor_ver = 0; + platf_cap->me_build_ver = 0; + platf_cap->me_hotfix_ver = 0; + } + + platf_cap->me_enabled = 1; + + me_fwcaps fw_caps; + if (mkhi_get_fwcaps(&fw_caps)) + { + if (fw_caps.caps_sku.kvm) + platf_cap->intel_kvm = 1; + } else { + platf_cap->intel_kvm = 0; + } + + me_platform_type platf_type; + if (mkhi_get_platform_type(&platf_type)) + { + switch (platf_type.brand) + { + case IntelAmtBrand: + platf_cap->intel_amt_fw = 1; + platf_cap->local_wakeup_timer = 1; + break; + + case IntelStandardManageabilityBrand: + platf_cap->intel_amt_fw_std = 1; + break; + } + } else { + platf_cap->intel_amt_fw = 0; + platf_cap->local_wakeup_timer = 0; + platf_cap->intel_amt_fw_std = 0; + } + + return; +} + + +void get_me_platf_config_state(u32 *config_state) +{ + u32 state = 0; + mefwcaps_sku fwcaps; + if (mkhi_get_fw_fea_state(&fwcaps)) + { + state |= fwcaps.full_net ? (1 << 8) : 0; + state |= fwcaps.std_net ? (1 << 9) : 0; + state |= fwcaps.manageability ? (1 << 10) : 0; + state |= fwcaps.integrated_touch ? (1 << 11) : 0; + state |= fwcaps.intel_cls ? (1 << 12) : 0; + state |= fwcaps.ish ? (1 << 13) : 0; + state |= fwcaps.pavp ? (1 << 14) : 0; + state |= fwcaps.ipv6 ? (1 << 15) : 0; + state |= fwcaps.kvm ? (1 << 16) : 0; + state |= fwcaps.dal ? (1 << 17) : 0; + state |= fwcaps.tls ? (1 << 18) : 0; + state |= fwcaps.wlan ? (1 << 19) : 0; + state |= fwcaps.ptt ? (1 << 20) : 0; + } + *config_state = state; + + return; +} + + +void get_network_device_lan(network_dev *nwk_dev) +{ + nwk_dev->function_number = PCI_FN_PCH_LAN; + nwk_dev->device_number = PCH_DEV_SLOT_LPC; + nwk_dev->bus_number = DEFAULT_PCI_BUS_NUMBER_PCH; + nwk_dev->device_id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + + return; +} + +void get_bios_sec_capab(bios_cap *bios_sec_cap) +{ + u32 cpu_feature_flag = cpuid(1).ecx; + if (cpu_feature_flag & CPUID_VMX) + { + bios_sec_cap->vtx_support = 1; + bios_sec_cap->vtd_support = 1; + } else { + bios_sec_cap->vtx_support = 0; + bios_sec_cap->vtd_support = 0; + } + + if (cpu_feature_flag & CPUID_SMX) + bios_sec_cap->txt_support = 1; + else + bios_sec_cap->txt_support = 0; + + return; +} + +void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131) +{ + + u32 cpu_capb = 0, bios_sec_cap = 0; + u64 pch_capb = 0, mebx_version = 0; + u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0}; + int i,j; + + /* CPU capabilities bits setting*/ + cpu_cap c_cap_data = me_info->cpu_capabilities; + cpu_capb |= (c_cap_data.vtx_enabled) ? (1 << 0) : 0; + cpu_capb |= (c_cap_data.lt_txt_cap) ? (1 << 1) : 0; + cpu_capb |= (c_cap_data.lt_txt_cap) ? (1 << 2) : 0; + cpu_capb |= (c_cap_data.lt_txt_enabled) ? (1 << 3) : 0; + cpu_capb |= (c_cap_data.vtx_cap) ? (1 << 4) : 0; + cpu_capb |= (c_cap_data.vtx_enabled) ? (1 << 5) : 0; + cpu_capb &= 0x3f; + type131->cpu_capability = cpu_capb; + + /* MEBx: ME BIOS Extensions bits setting*/ + u64 mask_0 = 0; + mebx_version |= me_info->mebx_version.major; + mebx_version |= (mask_0 | (me_info->mebx_version.minor)) << 16; + mebx_version |= (mask_0 | (me_info->mebx_version.hotfix)) << 32; + mebx_version |= (mask_0 | (me_info->mebx_version.build)) << 48; + type131->intel_mebx_version = mebx_version; + + /* PCH capabilities bits setting*/ + pch_cap ph_cap = me_info->pch_capabilities; + pch_capb |= ph_cap.function_number & BITS_0_THROUGH_2_MASK; + pch_capb |= (ph_cap.device_number << 3) & BITS_3_THROUGH_7_MASK; + pch_capb |= (ph_cap.bus_number << 8) & 0xff00; + pch_capb |= (ph_cap.device_id << 16) & WORD_1_MASK; + type131->pch_capability = pch_capb; + + /* ME platform capabilities bits setting */ + me_cap pf_cap = me_info->me_capabilities; + platf_cap[0] |= (pf_cap.me_enabled) ? 1: 0; + platf_cap[0] |= (pf_cap.intel_amt_fw) ? (1 << 3) : 0; + platf_cap[0] |= (pf_cap.intel_amt_fw_std) ? (1 << 4) : 0; + platf_cap[0] |= (pf_cap.intel_kvm) ? (1 << 14) : 0; + platf_cap[0] |= (pf_cap.local_wakeup_timer) ? (1 << 15) : 0; + platf_cap[1] |= pf_cap.me_minor_ver & WORD_0_MASK; + platf_cap[1] |= pf_cap.me_major_ver << 16; + platf_cap[2] |= pf_cap.me_build_ver & WORD_0_MASK; + platf_cap[2] |= pf_cap.me_hotfix_ver << 16; + + for (i=0; i < 3; i++) + memcpy(&type131->me_platf_capabilities[i], &platf_cap[i], 4); + + /* ME platform configuration state bits setting*/ + u32 config_state = 0; + get_me_platf_config_state(&config_state); + type131->me_feature_state = config_state; + + /* Network device LAN */ + network_dev net_dev = me_info->network_device; + nwk_dev_lan[0] |= net_dev.function_number & BITS_0_THROUGH_2_MASK; + nwk_dev_lan[0] |= (net_dev.device_number << 3) & BITS_3_THROUGH_7_MASK; + nwk_dev_lan[0] |= (net_dev.bus_number << 8) & 0xff00; + nwk_dev_lan[0] |= (net_dev.device_id << 16) & WORD_1_MASK; + nwk_dev_lan[1] = 0; + nwk_dev_lan[2] = 0; + for (j=0; j < 3; j++) + memcpy(&type131->network_device_lan[j],&nwk_dev_lan[j],4); + + /* BIOS securities capabilities bits setting */ + bios_cap b_cap = me_info->bios_sec_capab; + bios_sec_cap |= (b_cap.vtd_support) ? (1 << 1) : 0; + bios_sec_cap |= (b_cap.txt_support) ? (1 << 2) : 0; + bios_sec_cap |= (b_cap.vtx_support) ? (1 << 5) : 0; + type131->bios_sec_capabilities = bios_sec_cap; + + /* unique id for Intel vPro: vPro or 0x76 0x50 0x72 0x6F*/ + memcpy(&type131->structure_id, "vPro",4); + type131->reserved = 0; + + return; +} + +void save_me_smbios_info(me_smbios_info *me_info) +{ + /* CPU capabilities */ + get_me_cpu_capab(&me_info->cpu_capabilities); + + /* MEBx: ME BIOS Extensions */ + get_mebx_version(&me_info->mebx_version); + + /* PCH capabilities */ + get_pch_capab(&me_info->pch_capabilities); + + /* ME platform capabilities */ + get_me_platf_capab(&me_info->me_capabilities); + + /* ME platform configuration state */ + get_me_platf_config_state(&me_info->me_fw_config); + + /* Network device LAN */ + get_network_device_lan(&me_info->network_device); + + /* BIOS securities capabilities */ + get_bios_sec_capab(&me_info->bios_sec_capab); + + me_info->reserved = 0; + + return; +} + #if ENV_RAMSTAGE +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int smbios_write_type131_info(struct device *dev, int *handle, unsigned long *current) +{ + me_smbios_info me_info; + save_me_smbios_info(&me_info); + + struct smbios_type131 *t = (struct smbios_type131 *)*current; + int len = sizeof(struct smbios_type131); + + memset(t, 0, sizeof(struct smbios_type131)); + t->type = SMBIOS_INTEL_TYPE131; + t->length = len - 2; + t->handle = *handle; + + generate_type131_data(&me_info, t); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} +#endif + static void update_sec_bar(struct device *dev) { g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; @@ -511,6 +1025,9 @@ .read_resources = pci_dev_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_type131_info, +#endif .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index d7c4d9f..24b5927 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -47,4 +47,179 @@ #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 +typedef struct { + u32 vmx_state : 1; /* VMX state (On/Off) */ + u32 smx_state : 1; /* SMX state (On/Off) */ + u32 lt_txt_cap : 1; /* LT/TXT capability */ + u32 lt_txt_enabled : 1; /* LT/TXT Enabled state */ + u32 vtx_cap : 1; /* VT-x capability */ + u32 vtx_enabled : 1; /* VT-x Enabled state */ + u32 reserved : 26; +}__packed cpu_cap; + +typedef struct { + u32 function_number : 3; /* PCI Device Function Number */ + u32 device_number : 5; /* PCI Device Device Number */ + u32 bus_number : 8; /* PCI Device Bus Number */ + u32 device_id : 16; + u32 reserved : 32; +}__packed pch_cap; + +typedef struct { + u32 me_enabled : 1; /* ME enabled/Disabled */ + u32 reserved : 2; + u32 intel_amt_fw : 1; /* Intel AMT FW support */ + u32 intel_amt_fw_std : 1; /* Intel AMT Standard FW support */ + u32 reserved_1 : 9; + u32 intel_kvm : 1; /* Intel KVM supported */ + u32 local_wakeup_timer : 1; /* Local Wakeup Timer support */ + u32 reserved_2 : 16; + u32 me_minor_ver : 16; + u32 me_major_ver : 16; + u32 me_build_ver : 16; + u32 me_hotfix_ver : 16; +}__packed me_cap; + +typedef struct { + uint16_t code_minor; + uint16_t code_major; + uint16_t code_build_number; + uint16_t code_hot_fix; + uint16_t recovery_minor; + uint16_t recovery_major; + uint16_t recovery_build_number; + uint16_t recovery_hot_fix; + uint16_t fitcminor; + uint16_t fitcmajor; + uint16_t fitcbuildno; + uint16_t fitchotfix; +} __packed me_fw_version; + +typedef struct { + uint32_t full_net : 1; /* Full Network manageability */ + uint32_t std_net : 1; /* Regular Network manageability */ + uint32_t manageability : 1; /* Manageability */ + uint32_t reserved_1 : 1; + u32 integrated_touch : 1; /* Intel Integrated Touch */ + uint32_t reserved_2 : 1; + uint32_t intel_cls : 1; /* IntelR Capab Licensing Service */ + uint32_t reserved_3 : 3; + u32 ish : 1; /* IntelR Sensor Hub */ + uint32_t reserve_4 : 1; + uint32_t pavp : 1; /* Protected Audio Video Path (PAVP) */ + uint32_t reserved_5 : 4; + uint32_t ipv6 : 1; + uint32_t kvm : 1; + uint32_t reserve_6 : 1; + u32 dal : 1; /* Dynamic Application Loader (DAL) */ + u32 tls : 1; /* [21] Cipher Transport Layer (TLS) */ + uint32_t reserve_7 : 1; + uint32_t wlan : 1; /* Wireless LAN (WLAN) */ + uint32_t reserve_8 : 1; + uint32_t ptt : 1; /* Platform Trust Technology */ + uint32_t reserved_9 : 2; +}__packed mefwcaps_sku; + +typedef struct { + uint32_t id; + uint8_t length; + mefwcaps_sku caps_sku; + uint32_t reserved :3; +} __packed me_fwcaps; + + +/* Platform Type */ +typedef enum { + NoBrand, + IntelAmtBrand, + IntelStandardManageabilityBrand, + IntelReservedBrand1, + IntelReservedBrand2, + IntelReservedBrand3 +} platform_brand; + +typedef struct { + u32 function_number : 3; + u32 device_number : 5; + u32 bus_number : 8; + u32 device_id : 16; + u32 reserved1 : 16; + u32 reserved2 : 16; + u32 reserved3 : 32; +}__packed network_dev; + +typedef struct { + u32 reserved1 : 1; + u32 vtd_support : 1; ///< [1] BIOS supports VT-d + u32 txt_support : 1; ///< [2] BIOS supports TXT + u32 reserved2 : 1; + u32 reserved3 : 1; + u32 vtx_support : 1; ///< [5] BIOS supports VT-x + u32 reserved4 : 26; +}__packed bios_cap; + +typedef struct { + u16 major; + u16 minor; + u16 hotfix; + u16 build; +}__packed mebx_ver; + +typedef struct { + u32 mobile: 1; + u32 desktop: 1; + u32 server: 1; + u32 workstation: 1; + u32 corporate: 1; + u32 consumer: 1; + u32 regular_super_sku: 1; + u32 rsvd: 1; + u32 image_type: 4; + u32 brand: 4; + u32 rsvd1: 16; +} __packed me_platform_type; + +/* This is definition for SMBIOS Oem data type 131 */ +typedef struct { + cpu_cap cpu_capabilities; + mebx_ver mebx_version; + pch_cap pch_capabilities; + me_cap me_capabilities; + u32 me_fw_config; + network_dev network_device; + bios_cap bios_sec_capab; + u8 structure_identifier[4]; + u32 reserved; +}__packed me_smbios_info; + +struct smbios_type131 { + u8 type; + u8 length; + u16 handle; + u32 cpu_capability; + u64 intel_mebx_version; + u64 pch_capability; + u32 me_platf_capabilities[3]; + u32 me_feature_state; + u32 network_device_lan[3]; + u32 bios_sec_capabilities; + u32 structure_id; + u32 reserved; + u8 eos[2]; +}__packed ; + +int mkhi_get_fw_version(me_fw_version *version); +int mkhi_get_platform_type(me_platform_type *platf_type); +int mkhi_get_fw_fea_state(mefwcaps_sku *f_cap); +int mkhi_get_fwcaps(me_fwcaps *f_cap); +void get_me_cpu_capab(cpu_cap *cpu_capabilities); +void get_mebx_version(mebx_ver *mebx_verion); +void get_pch_capab(pch_cap *pch_capabilities); +void get_me_platf_capab(me_cap *platf_cap); +void get_me_platf_config_state(u32 *config_state); +void get_network_device_lan(network_dev *nwk_dev); +void get_bios_sec_capab(bios_cap *bios_sec_cap); +void save_me_smbios_info(me_smbios_info *me_info); +void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131); + #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/33067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida4e1a95e20289fbab01e773c18e00ce74aa8223 Gerrit-Change-Number: 33067 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add display hardware pipe line initialization [patch 3 of 3]
by mturney mturney (Code Review) 21 Jun '19

21 Jun '19

mturney mturney has uploaded a new patch set (#42) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/27588 ) Change subject: sdm845: Add display hardware pipe line initialization [patch 3 of 3] ...................................................................... sdm845: Add display hardware pipe line initialization [patch 3 of 3] Add sdm845 display hardware pipeline programming support and invoke the display initialization from soc_init for cheza boards. Change-Id: I432095d177bbbcfc1a00dc5db506f9736feef558 Signed-off-by: Sravan Kumar D.V.N <sravank1(a)codeaurora.org> --- M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/display.c A src/soc/qualcomm/sdm845/display/mdss.c A src/soc/qualcomm/sdm845/display/oem_panel.c A src/soc/qualcomm/sdm845/include/soc/display.h A src/soc/qualcomm/sdm845/include/soc/display/panel_sn65dsix6_2k_innolux_dsi_video.h M src/soc/qualcomm/sdm845/soc.c 8 files changed, 1,503 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27588/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/27588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432095d177bbbcfc1a00dc5db506f9736feef558 Gerrit-Change-Number: 27588 Gerrit-PatchSet: 42 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sravan Kumar Deepala <sravank(a)qti-qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sdm845: Add UART support
by mturney mturney (Code Review) 21 Jun '19

21 Jun '19

mturney mturney has uploaded a new patch set (#75) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/25373 ) Change subject: sdm845: Add UART support ...................................................................... sdm845: Add UART support TEST=build & run Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org> Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/mainboard/google/cheza/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h M src/soc/qualcomm/sdm845/qcom_qup_se.c A src/soc/qualcomm/sdm845/uart.c 6 files changed, 212 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/25373/75 -- To view, visit https://review.coreboot.org/c/coreboot/+/25373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Gerrit-Change-Number: 25373 Gerrit-PatchSet: 75 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2019