coreboot-gerrit June 2019

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Change in ...coreboot[master]: Move -Wlogical-op into xcompile
by Nico Huber (Code Review) 21 Jun '19

21 Jun '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33579 Change subject: Move -Wlogical-op into xcompile ...................................................................... Move -Wlogical-op into xcompile Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where we can easily check if it's supported. Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc M util/xcompile/xcompile 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/33579/1 diff --git a/Makefile.inc b/Makefile.inc index 48879bc..7ac0a82 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -401,7 +401,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wlogical-op +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 7ab1cb7..052b88f 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -203,6 +203,9 @@ CFLAGS_GCC+=" -EL" ;; esac + + # Generally available in GCC but not in Clang: + CFLAGS_GCC="$CFLAGS_GCC -Wlogical-op" } detect_compiler_runtime() { -- To view, visit https://review.coreboot.org/c/coreboot/+/33579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd Gerrit-Change-Number: 33579 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201/smihandler.c: Remove useless smihandler code
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33508 Change subject: mb/lenovo/x201/smihandler.c: Remove useless smihandler code ...................................................................... mb/lenovo/x201/smihandler.c: Remove useless smihandler code This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/smihandler.c 1 file changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/33508/1 diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 9043f8e..8d2a966 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -71,23 +71,6 @@ return 1; } -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -100,14 +83,6 @@ printk(BIOS_DEBUG, "EC event %02x\n", event); switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; case 0x18: /* Fn-F9 key */ case 0x27: -- To view, visit https://review.coreboot.org/c/coreboot/+/33508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6 Gerrit-Change-Number: 33508 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/*/{x201,packardbell}: Remove unused C-state generation functions
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33140 Change subject: mb/*/{x201,packardbell}: Remove unused C-state generation functions ...................................................................... mb/*/{x201,packardbell}: Remove unused C-state generation functions Those are copied from Lenovo X60 code, but are unused. NOTE: No ACPI C-state are generated on this platform but Linux has a separate driver for that. Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c 2 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33140/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index b8129ad..54acca3 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -29,19 +29,6 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <drivers/lenovo/lenovo.h> -#include <arch/acpigen.h> - -static acpi_cstate_t cst_entries[] = { - {1, 1, 1000, {0x7f, 1, 2, 0, 1, 0} }, - {2, 1, 500, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0} }, - {2, 17, 250, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0} }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} static void mainboard_init(struct device *dev) { diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 09310ae..28d3bb0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -24,7 +24,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> -#include <arch/acpigen.h> #include <drivers/intel/gma/int15.h> #include <arch/interrupt.h> #include <pc80/keyboard.h> @@ -32,20 +31,6 @@ #include <device/pci.h> #include <smbios.h> -static acpi_cstate_t cst_entries[] = { - {1, 1, 1000, {0x7f, 1, 2, 0, 1, 0} }, - {2, 1, 500, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0} }, - {2, 17, 250, {0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0} }, -}; - -int get_cst_entries(acpi_cstate_t ** entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - - - static void mainboard_enable(struct device *dev) { u16 pmbase; -- To view, visit https://review.coreboot.org/c/coreboot/+/33140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Gerrit-Change-Number: 33140 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/ibexpeak/smihandler: Move finalizing to a common location
by Arthur Heymans (Code Review) 21 Jun '19

21 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33139 Change subject: sb/intel/ibexpeak/smihandler: Move finalizing to a common location ...................................................................... sb/intel/ibexpeak/smihandler: Move finalizing to a common location TODO: There is no reason to do this in SMM. Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/packardbell/ms2290/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 3 files changed, 7 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33139/1 diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index fc6a0e9..9043f8e 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -20,10 +20,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/finalize.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> @@ -135,25 +132,9 @@ mainboard_smi_handle_ec_sci(); } -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 data) { switch (data) { - case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "APMC: FINALIZE\n"); - if (mainboard_finalized) { - printk(BIOS_DEBUG, "APMC#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); - intel_model_2065x_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 83562be..dfc66f9 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -18,11 +18,8 @@ #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/nvs.h> -#include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> static void mainboard_smm_init(void) @@ -54,26 +51,10 @@ { } -static int mainboard_finalized = 0; - int mainboard_smi_apmc(u8 data) { u8 tmp; switch (data) { - case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "APMC: FINALIZE\n"); - if (mainboard_finalized) { - printk(BIOS_DEBUG, "APMC#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); - intel_model_2065x_finalize_smm(); - - mainboard_finalized = 1; - break; case APM_CNT_ACPI_ENABLE: tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index dbc412c..208075b 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -24,7 +24,10 @@ #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/ibexpeak/me.h> #include "pch.h" #include "nvs.h" @@ -182,4 +185,8 @@ void southbridge_finalize_all(void) { + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_nehalem_finalize_smm(); + intel_model_2065x_finalize_smm(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Gerrit-Change-Number: 33139 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm/Makefile.inc: Remove VBOOT dependency for tss files in p...
by Frans Hendriks (Code Review) 21 Jun '19

21 Jun '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33444 Change subject: security/tpm/Makefile.inc: Remove VBOOT dependency for tss files in postcar ...................................................................... security/tpm/Makefile.inc: Remove VBOOT dependency for tss files in postcar tss_marshaling.c and tss.c depends on VBOOT for postcar. Eltan vendorcode used function in these file, but has VBOOT disabled. Remove depency of VBOOT for postcar fo tss/tcg-2.0/tss-marshaling.c and tss/tcg-2.0/tss.c BUG=N/A TEST=Created binary and verify logging on Facebook FBG-1701 Change-Id: I195c79283abf403208f406518372bf52289772ed Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/33444/1 diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index c05fb55..a2d32cf 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -36,8 +36,8 @@ verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c -postcar-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c +postcar-y += tss/tcg-2.0/tss_marshaling.c +postcar-y += tss/tcg-2.0/tss.c ## TSPI -- To view, visit https://review.coreboot.org/c/coreboot/+/33444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195c79283abf403208f406518372bf52289772ed Gerrit-Change-Number: 33444 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: mediatek/mt8183: Add infra group DCM setting
by Weiyi Lu (Code Review) 21 Jun '19

21 Jun '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31977 to review the following change. Change subject: WIP: mediatek/mt8183: Add infra group DCM setting ...................................................................... WIP: mediatek/mt8183: Add infra group DCM setting Add infra group DCM setting BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/pll.h M src/soc/mediatek/mt8183/pll.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31977/1 diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 5a5f58d..d1c7cd1 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -270,4 +270,13 @@ SPI_HZ = MAINPLL_D5_D2_HZ, }; +enum { + DCM_INFRA_BUS_MASK = 0x40907ffb, + DCM_INFRA_BUS_ON = 0x40900843, + DCM_INFRA_MEM_ON = 0x1 << 27, + DCM_INFRA_P2PRX_MASK = 0xf, + DCM_INFRA_PERI_MASK = 0xf03ffffb, + DCM_INFRA_PERI_ON = 0xf03f83e3, +}; + #endif /* SOC_MEDIATEK_MT8183_PLL_H */ diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de..4157c1d 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -344,6 +344,12 @@ /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, DCM_INFRA_BUS_MASK, + DCM_INFRA_BUS_ON); + setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, DCM_INFRA_PERI_MASK, + DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); -- To view, visit https://review.coreboot.org/c/coreboot/+/31977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Gerrit-Change-Number: 31977 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/driver/vpd: Update vpd_decode from upstream
by Hung-Te Lin (Code Review) 21 Jun '19

21 Jun '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33414 Change subject: src/driver/vpd: Update vpd_decode from upstream ...................................................................... src/driver/vpd: Update vpd_decode from upstream The upstream vpd_decode.c has been revised to prevent overrun of decoded contents. BUG=chromium:967209 TEST=select VPD config on kukui; make; boots on at least kukui boards. Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/drivers/vpd/vpd_decode.c M src/drivers/vpd/vpd_decode.h 2 files changed, 31 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33414/1 diff --git a/src/drivers/vpd/vpd_decode.c b/src/drivers/vpd/vpd_decode.c index 0eab704..e717972 100644 --- a/src/drivers/vpd/vpd_decode.c +++ b/src/drivers/vpd/vpd_decode.c @@ -8,7 +8,7 @@ */ #include "vpd_decode.h" -int vpd_decode_len( +static int vpd_decode_len( const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len) { u8 more; @@ -32,15 +32,36 @@ return VPD_DECODE_OK; } +static int vpd_decode_entry( + const u32 max_len, const u8 *input_buf, u32 *consumed, + const u8 **entry, u32 *entry_len) +{ + u32 decoded_len; + + if (vpd_decode_len(max_len - *consumed, &input_buf[*consumed], + entry_len, &decoded_len) != VPD_DECODE_OK) + return VPD_DECODE_FAIL; + if (max_len - *consumed < decoded_len) + return VPD_DECODE_FAIL; + + *consumed += decoded_len; + *entry = input_buf + *consumed; + + /* entry_len is untrusted data and must be checked again. */ + if (max_len - *consumed < *entry_len) + return VPD_DECODE_FAIL; + + *consumed += *entry_len; + return VPD_DECODE_OK; +} + int vpd_decode_string( const u32 max_len, const u8 *input_buf, u32 *consumed, vpd_decode_callback callback, void *callback_arg) { int type; - int res; u32 key_len; u32 value_len; - u32 decoded_len; const u8 *key; const u8 *value; @@ -55,33 +76,18 @@ case VPD_TYPE_STRING: (*consumed)++; - /* key */ - res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], - &key_len, &decoded_len); - /* key name cannot be empty, and must be followed by value. */ - if (res != VPD_DECODE_OK || key_len < 1 || - *consumed + decoded_len + key_len >= max_len) + if (vpd_decode_entry(max_len, input_buf, consumed, &key, + &key_len) != VPD_DECODE_OK) return VPD_DECODE_FAIL; - *consumed += decoded_len; - key = &input_buf[*consumed]; - *consumed += key_len; - - /* value */ - res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], - &value_len, &decoded_len); - /* value can be empty (value_len = 0). */ - if (res != VPD_DECODE_OK || - *consumed + decoded_len + value_len > max_len) + if (vpd_decode_entry(max_len, input_buf, consumed, &value, + &value_len) != VPD_DECODE_OK) return VPD_DECODE_FAIL; - *consumed += decoded_len; - value = &input_buf[*consumed]; - *consumed += value_len; - if (type == VPD_TYPE_STRING) return callback(key, key_len, value, value_len, callback_arg); + break; default: diff --git a/src/drivers/vpd/vpd_decode.h b/src/drivers/vpd/vpd_decode.h index 99ca7ef..5d595f3 100644 --- a/src/drivers/vpd/vpd_decode.h +++ b/src/drivers/vpd/vpd_decode.h @@ -30,28 +30,11 @@ void *arg); /* - * vpd_decode_len - * - * Given an encoded string, this function extracts the length of content - * (either key or value). The *consumed will contain the number of bytes - * consumed. - * - * The input_buf points to the first byte of the input buffer. - * - * The *consumed starts from 0, which is actually the next byte to be decoded. - * It can be non-zero to be used in multiple calls. - * - * Returns VPD_DECODE_OK on success, otherwise VPD_DECODE_FAIL. - */ -int vpd_decode_len( - const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len); - -/* * vpd_decode_string * * Given the encoded string, this function invokes callback with extracted - * (key, value). The *consumed will be plused the number of bytes consumed in - * this function. + * (key, value). The *consumed will be incremented by the number of bytes + * consumed in this function. * * The input_buf points to the first byte of the input buffer. * -- To view, visit https://review.coreboot.org/c/coreboot/+/33414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982 Gerrit-Change-Number: 33414 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl5: Change PTN interface settings
by Mario Scheithauer (Code Review) 21 Jun '19

21 Jun '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33196 Change subject: siemens/mc_apl5: Change PTN interface settings ...................................................................... siemens/mc_apl5: Change PTN interface settings Switch the clock output for single LVDS mode to odd bus only. Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33196/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index c0770f3..c655218 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -76,7 +76,8 @@ return (PTN_BUS_ERROR | status); /* Set up configuration data according to the hwinfo block we get. */ cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; + /* Use odd-bus for clock distribution only. */ + cfg.lvds_interface_ctrl1 = 0x01; if (disp_con == PF_DISPLCON_LVDS_DUAL) /* Turn on dual LVDS lane and clock. */ cfg.lvds_interface_ctrl1 |= 0x0b; -- To view, visit https://review.coreboot.org/c/coreboot/+/33196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Gerrit-Change-Number: 33196 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl5: Enable TPM support
by Mario Scheithauer (Code Review) 21 Jun '19

21 Jun '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33173 Change subject: siemens/mc_apl5: Enable TPM support ...................................................................... siemens/mc_apl5: Enable TPM support This patch enables TPM on SPI and adds the needed devicetree entry for mc_apl5. TEST=Build coreboot for mc_apl5 board and check the TPM console output. In addition the TPM was correctly verified by our Linux driver. Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c 3 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33173/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 196176c..4a4b6cc 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -8,5 +8,8 @@ select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select TPM_ON_FAST_SPI endif # BOARD_SIEMENS_MC_APL5 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index f1ed5d2..5f1c985 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -104,7 +104,11 @@ device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.1 on end # - SMBUS end end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 1dcd4f9..2ae65ec 100755 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -254,7 +254,7 @@ /* SIO_SPI_0 -- unused */ PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ - PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc Gerrit-Change-Number: 33173 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Modify SPI speed and tick_dly
by Mengqi Zhang (Code Review) 21 Jun '19

21 Jun '19

Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32462 Change subject: google/kukui: Modify SPI speed and tick_dly ...................................................................... google/kukui: Modify SPI speed and tick_dly To support high-speed boot process, speed up spi and set suitable tick_dly BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a Signed-off-by: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> --- M src/mainboard/google/kukui/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32462/1 diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 1efbc7a..232e17b 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -20,6 +20,6 @@ { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, 0); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, - 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 56 * MHz, + 2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a Gerrit-Change-Number: 32462 Gerrit-PatchSet: 1 Gerrit-Owner: Mengqi Zhang <Mengqi.Zhang(a)mediatek.com> Gerrit-MessageType: newchange

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